tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: FSL/NXP Integrated Flash Controller
8
9maintainers:
10 - Shawn Guo <shawnguo@kernel.org>
11
12description: |
13 NXP's integrated flash controller (IFC) is an advanced version of the
14 enhanced local bus controller which includes similar programming and signal
15 interfaces with an extended feature set. The IFC provides access to multiple
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
17 SRAM and other memories where address and data are shared on a bus.
18
19properties:
20 $nodename:
21 pattern: "^memory-controller@[0-9a-f]+$"
22
23 compatible:
24 const: fsl,ifc
25
26 "#address-cells":
27 enum: [2, 3]
28 description: |
29 Should be either two or three. The first cell is the chipselect
30 number, and the remaining cells are the offset into the chipselect.
31
32 "#size-cells":
33 enum: [1, 2]
34 description: |
35 Either one or two, depending on how large each chipselect can be.
36
37 reg:
38 maxItems: 1
39
40 interrupts:
41 minItems: 1
42 maxItems: 2
43 description: |
44 IFC may have one or two interrupts. If two interrupt specifiers are
45 present, the first is the "common" interrupt (CM_EVTER_STAT), and the
46 second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
47 that interrupt reports both types of event.
48
49 little-endian:
50 type: boolean
51 description: |
52 If this property is absent, the big-endian mode will be in use as default
53 for registers.
54
55 ranges:
56 description: |
57 Each range corresponds to a single chipselect, and covers the entire
58 access window as configured.
59
60patternProperties:
61 "^nand@[a-f0-9]+(,[a-f0-9]+)+$":
62 type: object
63 properties:
64 compatible:
65 const: fsl,ifc-nand
66
67 reg:
68 maxItems: 1
69
70 "#address-cells":
71 const: 1
72
73 "#size-cells":
74 const: 1
75
76 patternProperties:
77 "^partition@[0-9a-f]+":
78 $ref: /schemas/mtd/partitions/partition.yaml#
79 deprecated: true
80
81 required:
82 - compatible
83 - reg
84
85 additionalProperties: false
86
87 "(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$":
88 type: object
89 oneOf:
90 - $ref: /schemas/board/fsl,fpga-qixis.yaml#
91 - $ref: /schemas/mtd/mtd-physmap.yaml#
92 unevaluatedProperties: false
93
94required:
95 - compatible
96 - reg
97 - interrupts
98
99additionalProperties: false
100
101examples:
102 - |
103 soc {
104 #address-cells = <2>;
105 #size-cells = <2>;
106
107 memory-controller@ffe1e000 {
108 compatible = "fsl,ifc";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 reg = <0x0 0xffe1e000 0 0x2000>;
112 interrupts = <16 2 19 2>;
113 little-endian;
114
115 /* NOR, NAND Flashes and CPLD on board */
116 ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
117 <0x1 0x0 0x0 0xffa00000 0x00010000>,
118 <0x3 0x0 0x0 0xffb00000 0x00020000>;
119
120 flash@0,0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "cfi-flash";
124 reg = <0x0 0x0 0x2000000>;
125 bank-width = <2>;
126 device-width = <1>;
127
128 partition@0 {
129 /* 32MB for user data */
130 reg = <0x0 0x02000000>;
131 label = "NOR Data";
132 };
133 };
134 };
135 };