tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments gate clock
8
9maintainers:
10 - Tero Kristo <kristo@kernel.org>
11
12description: |
13 *Deprecated design pattern: one node per clock*
14
15 This clock is quite much similar to the basic gate-clock [1], however,
16 it supports a number of additional features. If no register
17 is provided for this clock, the code assumes that a clockdomain
18 will be controlled instead and the corresponding hw-ops for
19 that is used.
20
21 [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
22 [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
23
24properties:
25 compatible:
26 enum:
27 - ti,gate-clock # basic gate clock
28 - ti,wait-gate-clock # gate clock which waits until clock is
29 # active before returning from clk_enable()
30 - ti,dss-gate-clock # gate clock with DSS specific hardware
31 # handling
32 - ti,am35xx-gate-clock # gate clock with AM35xx specific hardware
33 # handling
34 - ti,clkdm-gate-clock # clockdomain gate clock, which derives its
35 # functional clock directly from a
36 # clockdomain, see [2] how to map
37 # clockdomains properly
38 - ti,hsdiv-gate-clock # gate clock with OMAP36xx specific hardware
39 # handling, required for a hardware errata
40 - ti,composite-gate-clock # composite gate clock, to be part of
41 # composite clock
42 - ti,composite-no-wait-gate-clock # composite gate clock that does not
43 # wait for clock to be active before
44 # returning from clk_enable()
45 "#clock-cells":
46 const: 0
47
48 clocks: true
49
50 clock-output-names:
51 maxItems: 1
52
53 reg:
54 maxItems: 1
55
56 ti,bit-shift:
57 $ref: /schemas/types.yaml#/definitions/uint32
58 description:
59 Number of bits to shift the bit-mask
60 maximum: 31
61 default: 0
62
63 ti,set-bit-to-disable:
64 type: boolean
65 description:
66 Inverts default gate programming. Setting the bit
67 gates the clock and clearing the bit ungates the clock.
68
69 ti,set-rate-parent:
70 type: boolean
71 description:
72 clk_set_rate is propagated to parent clock,
73
74if:
75 properties:
76 compatible:
77 contains:
78 const: ti,clkdm-gate-clock
79then:
80 properties:
81 reg: false
82 required:
83 - compatible
84 - "#clock-cells"
85 - clocks
86else:
87 required:
88 - compatible
89 - "#clock-cells"
90 - clocks
91 - reg
92
93additionalProperties: false
94
95examples:
96 - |
97 bus {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 clock-controller@a00 {
102 #clock-cells = <0>;
103 compatible = "ti,gate-clock";
104 clocks = <&core_96m_fck>;
105 reg = <0x0a00>;
106 ti,bit-shift = <25>;
107 };
108
109 clock-controller@d00 {
110 compatible = "ti,hsdiv-gate-clock";
111 reg = <0x0d00>;
112 #clock-cells = <0>;
113 clocks = <&dpll4_m2x2_mul_ck>;
114 ti,bit-shift = <0x1b>;
115 ti,set-bit-to-disable;
116 };
117 };
118
119 - |
120 clock-controller {
121 #clock-cells = <0>;
122 compatible = "ti,clkdm-gate-clock";
123 clocks = <&emu_src_mux_ck>;
124 };
125