tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Get values of vector registers as soon as the program starts to test if
4 * is properly cleaning the values before starting a new program. Vector
5 * registers are caller saved, so no function calls may happen before reading
6 * the values. To further ensure consistency, this file is compiled without
7 * libc and without auto-vectorization.
8 *
9 * To be "clean" all values must be all zeroes.
10 */
11
12#define __stringify_1(x...) #x
13#define __stringify(x...) __stringify_1(x)
14
15int main(int argc, char **argv)
16{
17 char value = 0;
18 unsigned long vl;
19
20 if (argc > 2 && strcmp(argv[2], "x"))
21 asm volatile (
22 // 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
23 // vsetvli t4, x0, e8, m1, d1
24 ".4byte 0b00000000000000000111111011010111\n\t"
25 "mv %[vl], t4\n\t"
26 : [vl] "=r" (vl) : : "t4"
27 );
28 else
29 asm volatile (
30 ".option push\n\t"
31 ".option arch, +v\n\t"
32 "vsetvli %[vl], x0, e8, m1, ta, ma\n\t"
33 ".option pop\n\t"
34 : [vl] "=r" (vl)
35 );
36
37#define CHECK_VECTOR_REGISTER(register) ({ \
38 for (int i = 0; i < vl; i++) { \
39 asm volatile ( \
40 ".option push\n\t" \
41 ".option arch, +v\n\t" \
42 "vmv.x.s %0, " __stringify(register) "\n\t" \
43 "vsrl.vi " __stringify(register) ", " __stringify(register) ", 8\n\t" \
44 ".option pop\n\t" \
45 : "=r" (value)); \
46 if (value != 0x00) { \
47 printf("Register " __stringify(register) \
48 " values not clean! value: %u\n", value); \
49 exit(-1); \
50 } \
51 } \
52})
53
54 CHECK_VECTOR_REGISTER(v0);
55 CHECK_VECTOR_REGISTER(v1);
56 CHECK_VECTOR_REGISTER(v2);
57 CHECK_VECTOR_REGISTER(v3);
58 CHECK_VECTOR_REGISTER(v4);
59 CHECK_VECTOR_REGISTER(v5);
60 CHECK_VECTOR_REGISTER(v6);
61 CHECK_VECTOR_REGISTER(v7);
62 CHECK_VECTOR_REGISTER(v8);
63 CHECK_VECTOR_REGISTER(v9);
64 CHECK_VECTOR_REGISTER(v10);
65 CHECK_VECTOR_REGISTER(v11);
66 CHECK_VECTOR_REGISTER(v12);
67 CHECK_VECTOR_REGISTER(v13);
68 CHECK_VECTOR_REGISTER(v14);
69 CHECK_VECTOR_REGISTER(v15);
70 CHECK_VECTOR_REGISTER(v16);
71 CHECK_VECTOR_REGISTER(v17);
72 CHECK_VECTOR_REGISTER(v18);
73 CHECK_VECTOR_REGISTER(v19);
74 CHECK_VECTOR_REGISTER(v20);
75 CHECK_VECTOR_REGISTER(v21);
76 CHECK_VECTOR_REGISTER(v22);
77 CHECK_VECTOR_REGISTER(v23);
78 CHECK_VECTOR_REGISTER(v24);
79 CHECK_VECTOR_REGISTER(v25);
80 CHECK_VECTOR_REGISTER(v26);
81 CHECK_VECTOR_REGISTER(v27);
82 CHECK_VECTOR_REGISTER(v28);
83 CHECK_VECTOR_REGISTER(v29);
84 CHECK_VECTOR_REGISTER(v30);
85 CHECK_VECTOR_REGISTER(v31);
86
87#undef CHECK_VECTOR_REGISTER
88
89 return 0;
90}