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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Composable Cache Controller
9
10maintainers:
11 - Paul Walmsley <paul.walmsley@sifive.com>
12
13description:
14 The SiFive Composable Cache Controller is used to provide access to fast copies
15 of memory for masters in a Core Complex. The Composable Cache Controller also
16 acts as directory-based coherency manager.
17 All the properties in ePAPR/DeviceTree specification applies for this platform.
18
19select:
20 properties:
21 compatible:
22 contains:
23 enum:
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
27
28 required:
29 - compatible
30
31properties:
32 compatible:
33 oneOf:
34 - items:
35 - enum:
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
38 - sifive,fu740-c000-ccache
39 - const: cache
40 - items:
41 - enum:
42 - eswin,eic7700-l3-cache
43 - starfive,jh7100-ccache
44 - starfive,jh7110-ccache
45 - const: sifive,ccache0
46 - const: cache
47 - items:
48 - const: microchip,mpfs-ccache
49 - const: sifive,fu540-c000-ccache
50 - const: cache
51
52 cache-block-size:
53 const: 64
54
55 cache-level:
56 enum: [2, 3]
57
58 cache-sets:
59 enum: [1024, 2048, 4096]
60
61 cache-size:
62 enum: [2097152, 4194304]
63
64 cache-unified: true
65
66 interrupts:
67 minItems: 3
68 items:
69 - description: DirError interrupt
70 - description: DataError interrupt
71 - description: DataFail interrupt
72 - description: DirFail interrupt
73
74 reg:
75 maxItems: 1
76
77 next-level-cache: true
78
79 memory-region:
80 maxItems: 1
81 description: |
82 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
83 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
84
85allOf:
86 - $ref: /schemas/cache-controller.yaml#
87
88 - if:
89 properties:
90 compatible:
91 contains:
92 enum:
93 - eswin,eic7700-l3-cache
94 - sifive,fu740-c000-ccache
95 - starfive,jh7100-ccache
96 - starfive,jh7110-ccache
97 - microchip,mpfs-ccache
98
99 then:
100 properties:
101 interrupts:
102 description: |
103 Must contain entries for DirError, DataError, DataFail, DirFail signals.
104 minItems: 4
105
106 else:
107 properties:
108 interrupts:
109 description: |
110 Must contain entries for DirError, DataError and DataFail signals.
111 maxItems: 3
112
113 - if:
114 properties:
115 compatible:
116 contains:
117 const: eswin,eic7700-l3-cache
118
119 then:
120 properties:
121 cache-size:
122 const: 4194304
123
124 else:
125 properties:
126 cache-size:
127 const: 2097152
128
129 - if:
130 properties:
131 compatible:
132 contains:
133 enum:
134 - sifive,fu740-c000-ccache
135 - starfive,jh7100-ccache
136 - starfive,jh7110-ccache
137
138 then:
139 properties:
140 cache-sets:
141 const: 2048
142
143 - if:
144 properties:
145 compatible:
146 contains:
147 enum:
148 - microchip,mpfs-ccache
149 - sifive,fu540-c000-ccache
150
151 then:
152 properties:
153 cache-sets:
154 const: 1024
155
156 - if:
157 properties:
158 compatible:
159 contains:
160 enum:
161 - eswin,eic7700-l3-cache
162
163 then:
164 properties:
165 cache-sets:
166 const: 4096
167
168 - if:
169 properties:
170 compatible:
171 contains:
172 const: sifive,ccache0
173
174 then:
175 properties:
176 cache-level:
177 enum: [2, 3]
178
179 else:
180 properties:
181 cache-level:
182 const: 2
183
184additionalProperties: false
185
186required:
187 - compatible
188 - cache-block-size
189 - cache-level
190 - cache-sets
191 - cache-size
192 - cache-unified
193 - interrupts
194 - reg
195
196examples:
197 - |
198 cache-controller@2010000 {
199 compatible = "sifive,fu540-c000-ccache", "cache";
200 cache-block-size = <64>;
201 cache-level = <2>;
202 cache-sets = <1024>;
203 cache-size = <2097152>;
204 cache-unified;
205 reg = <0x2010000 0x1000>;
206 interrupt-parent = <&plic0>;
207 interrupts = <1>,
208 <2>,
209 <3>;
210 next-level-cache = <&L25>;
211 memory-region = <&l2_lim>;
212 };