Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
29extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
30extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
31extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
32
33enum smu_event_type {
34 SMU_EVENT_RESET_COMPLETE = 0,
35};
36
37struct amd_vce_state {
38 /* vce clocks */
39 u32 evclk;
40 u32 ecclk;
41 /* gpu clocks */
42 u32 sclk;
43 u32 mclk;
44 u8 clk_idx;
45 u8 pstate;
46};
47
48
49enum amd_dpm_forced_level {
50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
52 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
60};
61
62enum amd_pm_state_type {
63 /* not used for dpm */
64 POWER_STATE_TYPE_DEFAULT,
65 POWER_STATE_TYPE_POWERSAVE,
66 /* user selectable states */
67 POWER_STATE_TYPE_BATTERY,
68 POWER_STATE_TYPE_BALANCED,
69 POWER_STATE_TYPE_PERFORMANCE,
70 /* internal states */
71 POWER_STATE_TYPE_INTERNAL_UVD,
72 POWER_STATE_TYPE_INTERNAL_UVD_SD,
73 POWER_STATE_TYPE_INTERNAL_UVD_HD,
74 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
75 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
76 POWER_STATE_TYPE_INTERNAL_BOOT,
77 POWER_STATE_TYPE_INTERNAL_THERMAL,
78 POWER_STATE_TYPE_INTERNAL_ACPI,
79 POWER_STATE_TYPE_INTERNAL_ULV,
80 POWER_STATE_TYPE_INTERNAL_3DPERF,
81};
82
83#define AMD_MAX_VCE_LEVELS 6
84
85enum amd_vce_level {
86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
92};
93
94enum amd_fan_ctrl_mode {
95 AMD_FAN_CTRL_NONE = 0,
96 AMD_FAN_CTRL_MANUAL = 1,
97 AMD_FAN_CTRL_AUTO = 2,
98};
99
100enum pp_clock_type {
101 PP_SCLK,
102 PP_MCLK,
103 PP_PCIE,
104 PP_SOCCLK,
105 PP_FCLK,
106 PP_DCEFCLK,
107 PP_VCLK,
108 PP_VCLK1,
109 PP_DCLK,
110 PP_DCLK1,
111 OD_SCLK,
112 OD_MCLK,
113 OD_VDDC_CURVE,
114 OD_RANGE,
115 OD_VDDGFX_OFFSET,
116 OD_CCLK,
117 OD_FAN_CURVE,
118 OD_ACOUSTIC_LIMIT,
119 OD_ACOUSTIC_TARGET,
120 OD_FAN_TARGET_TEMPERATURE,
121 OD_FAN_MINIMUM_PWM,
122 OD_FAN_ZERO_RPM_ENABLE,
123 OD_FAN_ZERO_RPM_STOP_TEMP,
124};
125
126enum amd_pp_sensors {
127 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
128 AMDGPU_PP_SENSOR_CPU_CLK,
129 AMDGPU_PP_SENSOR_VDDNB,
130 AMDGPU_PP_SENSOR_VDDGFX,
131 AMDGPU_PP_SENSOR_VDDBOARD,
132 AMDGPU_PP_SENSOR_UVD_VCLK,
133 AMDGPU_PP_SENSOR_UVD_DCLK,
134 AMDGPU_PP_SENSOR_VCE_ECCLK,
135 AMDGPU_PP_SENSOR_GPU_LOAD,
136 AMDGPU_PP_SENSOR_MEM_LOAD,
137 AMDGPU_PP_SENSOR_GFX_MCLK,
138 AMDGPU_PP_SENSOR_GPU_TEMP,
139 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
140 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
141 AMDGPU_PP_SENSOR_MEM_TEMP,
142 AMDGPU_PP_SENSOR_VCE_POWER,
143 AMDGPU_PP_SENSOR_UVD_POWER,
144 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
145 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
146 AMDGPU_PP_SENSOR_SS_APU_SHARE,
147 AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
148 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
149 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
150 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
151 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
152 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
153 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
154 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
155 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
156 AMDGPU_PP_SENSOR_VCN_LOAD,
157};
158
159enum amd_pp_task {
160 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
161 AMD_PP_TASK_ENABLE_USER_STATE,
162 AMD_PP_TASK_READJUST_POWER_STATE,
163 AMD_PP_TASK_COMPLETE_INIT,
164 AMD_PP_TASK_MAX
165};
166
167enum PP_SMC_POWER_PROFILE {
168 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
169 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
170 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
171 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
172 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
173 PP_SMC_POWER_PROFILE_VR = 0x4,
174 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
175 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
176 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7,
177 PP_SMC_POWER_PROFILE_CAPPED = 0x8,
178 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9,
179 PP_SMC_POWER_PROFILE_COUNT,
180};
181
182extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
183
184
185
186enum {
187 PP_GROUP_UNKNOWN = 0,
188 PP_GROUP_GFX = 1,
189 PP_GROUP_SYS,
190 PP_GROUP_MAX
191};
192
193enum PP_OD_DPM_TABLE_COMMAND {
194 PP_OD_EDIT_SCLK_VDDC_TABLE,
195 PP_OD_EDIT_MCLK_VDDC_TABLE,
196 PP_OD_EDIT_CCLK_VDDC_TABLE,
197 PP_OD_EDIT_VDDC_CURVE,
198 PP_OD_RESTORE_DEFAULT_TABLE,
199 PP_OD_COMMIT_DPM_TABLE,
200 PP_OD_EDIT_VDDGFX_OFFSET,
201 PP_OD_EDIT_FAN_CURVE,
202 PP_OD_EDIT_ACOUSTIC_LIMIT,
203 PP_OD_EDIT_ACOUSTIC_TARGET,
204 PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
205 PP_OD_EDIT_FAN_MINIMUM_PWM,
206 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
207 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
208};
209
210struct pp_states_info {
211 uint32_t nums;
212 uint32_t states[16];
213};
214
215enum PP_HWMON_TEMP {
216 PP_TEMP_EDGE = 0,
217 PP_TEMP_JUNCTION,
218 PP_TEMP_MEM,
219 PP_TEMP_MAX
220};
221
222enum pp_mp1_state {
223 PP_MP1_STATE_NONE,
224 PP_MP1_STATE_SHUTDOWN,
225 PP_MP1_STATE_UNLOAD,
226 PP_MP1_STATE_RESET,
227 PP_MP1_STATE_FLR,
228};
229
230enum pp_df_cstate {
231 DF_CSTATE_DISALLOW = 0,
232 DF_CSTATE_ALLOW,
233};
234
235/**
236 * DOC: amdgpu_pp_power
237 *
238 * APU power is managed to system-level requirements through the PPT
239 * (package power tracking) feature. PPT is intended to limit power to the
240 * requirements of the power source and could be dynamically updated to
241 * maximize APU performance within the system power budget.
242 *
243 * Two types of power measurement can be requested, where supported, with
244 * :c:type:`enum pp_power_type <pp_power_type>`.
245 */
246
247/**
248 * enum pp_power_limit_level - Used to query the power limits
249 *
250 * @PP_PWR_LIMIT_MIN: Minimum Power Limit
251 * @PP_PWR_LIMIT_CURRENT: Current Power Limit
252 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
253 * @PP_PWR_LIMIT_MAX: Maximum Power Limit
254 */
255enum pp_power_limit_level {
256 PP_PWR_LIMIT_MIN = -1,
257 PP_PWR_LIMIT_CURRENT,
258 PP_PWR_LIMIT_DEFAULT,
259 PP_PWR_LIMIT_MAX,
260};
261
262/**
263 * enum pp_power_type - Used to specify the type of the requested power
264 *
265 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
266 * moving average of APU power (default ~5000 ms).
267 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
268 * where supported.
269 */
270enum pp_power_type {
271 PP_PWR_TYPE_SUSTAINED,
272 PP_PWR_TYPE_FAST,
273};
274
275enum pp_xgmi_plpd_mode {
276 XGMI_PLPD_NONE = -1,
277 XGMI_PLPD_DISALLOW,
278 XGMI_PLPD_DEFAULT,
279 XGMI_PLPD_OPTIMIZED,
280 XGMI_PLPD_COUNT,
281};
282
283enum pp_pm_policy {
284 PP_PM_POLICY_NONE = -1,
285 PP_PM_POLICY_SOC_PSTATE = 0,
286 PP_PM_POLICY_XGMI_PLPD,
287 PP_PM_POLICY_NUM,
288};
289
290enum pp_policy_soc_pstate {
291 SOC_PSTATE_DEFAULT = 0,
292 SOC_PSTATE_0,
293 SOC_PSTATE_1,
294 SOC_PSTATE_2,
295 SOC_PSTAT_COUNT,
296};
297
298#define PP_POLICY_MAX_LEVELS 5
299
300#define PP_GROUP_MASK 0xF0000000
301#define PP_GROUP_SHIFT 28
302
303#define PP_BLOCK_MASK 0x0FFFFF00
304#define PP_BLOCK_SHIFT 8
305
306#define PP_BLOCK_GFX_CG 0x01
307#define PP_BLOCK_GFX_MG 0x02
308#define PP_BLOCK_GFX_3D 0x04
309#define PP_BLOCK_GFX_RLC 0x08
310#define PP_BLOCK_GFX_CP 0x10
311#define PP_BLOCK_SYS_BIF 0x01
312#define PP_BLOCK_SYS_MC 0x02
313#define PP_BLOCK_SYS_ROM 0x04
314#define PP_BLOCK_SYS_DRM 0x08
315#define PP_BLOCK_SYS_HDP 0x10
316#define PP_BLOCK_SYS_SDMA 0x20
317
318#define PP_STATE_MASK 0x0000000F
319#define PP_STATE_SHIFT 0
320#define PP_STATE_SUPPORT_MASK 0x000000F0
321#define PP_STATE_SUPPORT_SHIFT 0
322
323#define PP_STATE_CG 0x01
324#define PP_STATE_LS 0x02
325#define PP_STATE_DS 0x04
326#define PP_STATE_SD 0x08
327#define PP_STATE_SUPPORT_CG 0x10
328#define PP_STATE_SUPPORT_LS 0x20
329#define PP_STATE_SUPPORT_DS 0x40
330#define PP_STATE_SUPPORT_SD 0x80
331
332#define PP_CG_MSG_ID(group, block, support, state) \
333 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
334 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
335
336#define XGMI_MODE_PSTATE_D3 0
337#define XGMI_MODE_PSTATE_D0 1
338
339#define NUM_HBM_INSTANCES 4
340#define NUM_XGMI_LINKS 8
341#define MAX_GFX_CLKS 8
342#define MAX_CLKS 4
343#define NUM_VCN 4
344#define NUM_JPEG_ENG 32
345#define NUM_JPEG_ENG_V1 40
346#define MAX_XCC 8
347#define NUM_XCP 8
348struct seq_file;
349enum amd_pp_clock_type;
350struct amd_pp_simple_clock_info;
351struct amd_pp_display_configuration;
352struct amd_pp_clock_info;
353struct pp_display_clock_request;
354struct pp_clock_levels_with_voltage;
355struct pp_clock_levels_with_latency;
356struct amd_pp_clocks;
357struct pp_smu_wm_range_sets;
358struct pp_smu_nv_clock_table;
359struct dpm_clocks;
360
361struct amdgpu_xcp_metrics {
362 /* Utilization Instantaneous (%) */
363 uint32_t gfx_busy_inst[MAX_XCC];
364 uint16_t jpeg_busy[NUM_JPEG_ENG];
365 uint16_t vcn_busy[NUM_VCN];
366 /* Utilization Accumulated (%) */
367 uint64_t gfx_busy_acc[MAX_XCC];
368};
369
370struct amdgpu_xcp_metrics_v1_1 {
371 /* Utilization Instantaneous (%) */
372 uint32_t gfx_busy_inst[MAX_XCC];
373 uint16_t jpeg_busy[NUM_JPEG_ENG];
374 uint16_t vcn_busy[NUM_VCN];
375 /* Utilization Accumulated (%) */
376 uint64_t gfx_busy_acc[MAX_XCC];
377 /* Total App Clock Counter Accumulated */
378 uint64_t gfx_below_host_limit_acc[MAX_XCC];
379};
380
381struct amdgpu_xcp_metrics_v1_2 {
382 /* Utilization Instantaneous (%) */
383 uint32_t gfx_busy_inst[MAX_XCC];
384 uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
385 uint16_t vcn_busy[NUM_VCN];
386 /* Utilization Accumulated (%) */
387 uint64_t gfx_busy_acc[MAX_XCC];
388 /* Total App Clock Counter Accumulated */
389 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
390 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
391 uint64_t gfx_low_utilization_acc[MAX_XCC];
392 uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
393};
394
395struct amd_pm_funcs {
396/* export for dpm on ci and si */
397 int (*pre_set_power_state)(void *handle);
398 int (*set_power_state)(void *handle);
399 void (*post_set_power_state)(void *handle);
400 void (*display_configuration_changed)(void *handle);
401 void (*print_power_state)(void *handle, void *ps);
402 bool (*vblank_too_short)(void *handle);
403 void (*enable_bapm)(void *handle, bool enable);
404 int (*check_state_equal)(void *handle,
405 void *cps,
406 void *rps,
407 bool *equal);
408/* export for sysfs */
409 int (*set_fan_control_mode)(void *handle, u32 mode);
410 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
411 int (*set_fan_speed_pwm)(void *handle, u32 speed);
412 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
413 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
414 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
415 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
416 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
417 int (*get_sclk_od)(void *handle);
418 int (*set_sclk_od)(void *handle, uint32_t value);
419 int (*get_mclk_od)(void *handle);
420 int (*set_mclk_od)(void *handle, uint32_t value);
421 int (*read_sensor)(void *handle, int idx, void *value, int *size);
422 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
423 int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
424 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
425 enum amd_pm_state_type (*get_current_power_state)(void *handle);
426 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
427 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
428 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
429 int (*get_pp_table)(void *handle, char **table);
430 int (*set_pp_table)(void *handle, const char *buf, size_t size);
431 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
432 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
433 int (*pause_power_profile)(void *handle, bool pause);
434/* export to amdgpu */
435 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
436 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
437 enum amd_pm_state_type *user_state);
438 int (*load_firmware)(void *handle);
439 int (*wait_for_fw_loading_complete)(void *handle);
440 int (*set_powergating_by_smu)(void *handle,
441 uint32_t block_type,
442 bool gate,
443 int inst);
444 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
445 int (*set_power_limit)(void *handle, uint32_t n);
446 int (*get_power_limit)(void *handle, uint32_t *limit,
447 enum pp_power_limit_level pp_limit_level,
448 enum pp_power_type power_type);
449 int (*get_power_profile_mode)(void *handle, char *buf);
450 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
451 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
452 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
453 long *input, uint32_t size);
454 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
455 int (*smu_i2c_bus_access)(void *handle, bool acquire);
456 int (*gfx_state_change_set)(void *handle, uint32_t state);
457/* export to DC */
458 u32 (*get_sclk)(void *handle, bool low);
459 u32 (*get_mclk)(void *handle, bool low);
460 int (*display_configuration_change)(void *handle,
461 const struct amd_pp_display_configuration *input);
462 int (*get_display_power_level)(void *handle,
463 struct amd_pp_simple_clock_info *output);
464 int (*get_current_clocks)(void *handle,
465 struct amd_pp_clock_info *clocks);
466 int (*get_clock_by_type)(void *handle,
467 enum amd_pp_clock_type type,
468 struct amd_pp_clocks *clocks);
469 int (*get_clock_by_type_with_latency)(void *handle,
470 enum amd_pp_clock_type type,
471 struct pp_clock_levels_with_latency *clocks);
472 int (*get_clock_by_type_with_voltage)(void *handle,
473 enum amd_pp_clock_type type,
474 struct pp_clock_levels_with_voltage *clocks);
475 int (*set_watermarks_for_clocks_ranges)(void *handle,
476 void *clock_ranges);
477 int (*display_clock_voltage_request)(void *handle,
478 struct pp_display_clock_request *clock);
479 int (*get_display_mode_validation_clocks)(void *handle,
480 struct amd_pp_simple_clock_info *clocks);
481 int (*notify_smu_enable_pwe)(void *handle);
482 int (*enable_mgpu_fan_boost)(void *handle);
483 int (*set_active_display_count)(void *handle, uint32_t count);
484 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
485 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
486 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
487 int (*get_asic_baco_capability)(void *handle);
488 int (*get_asic_baco_state)(void *handle, int *state);
489 int (*set_asic_baco_state)(void *handle, int state);
490 int (*get_ppfeature_status)(void *handle, char *buf);
491 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
492 int (*asic_reset_mode_2)(void *handle);
493 int (*asic_reset_enable_gfx_features)(void *handle);
494 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
495 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
496 ssize_t (*get_gpu_metrics)(void *handle, void **table);
497 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table);
498 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
499 int (*set_watermarks_for_clock_ranges)(void *handle,
500 struct pp_smu_wm_range_sets *ranges);
501 int (*display_disable_memory_clock_switch)(void *handle,
502 bool disable_memory_clock_switch);
503 int (*get_max_sustainable_clocks_by_dc)(void *handle,
504 struct pp_smu_nv_clock_table *max_clocks);
505 int (*get_uclk_dpm_states)(void *handle,
506 unsigned int *clock_values_in_khz,
507 unsigned int *num_states);
508 int (*get_dpm_clock_table)(void *handle,
509 struct dpm_clocks *clock_table);
510 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
511 void (*pm_compute_clocks)(void *handle);
512 int (*notify_rlc_state)(void *handle, bool en);
513};
514
515struct metrics_table_header {
516 uint16_t structure_size;
517 uint8_t format_revision;
518 uint8_t content_revision;
519};
520
521/*
522 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
523 * Use gpu_metrics_v1_1 or later instead.
524 */
525struct gpu_metrics_v1_0 {
526 struct metrics_table_header common_header;
527
528 /* Driver attached timestamp (in ns) */
529 uint64_t system_clock_counter;
530
531 /* Temperature */
532 uint16_t temperature_edge;
533 uint16_t temperature_hotspot;
534 uint16_t temperature_mem;
535 uint16_t temperature_vrgfx;
536 uint16_t temperature_vrsoc;
537 uint16_t temperature_vrmem;
538
539 /* Utilization */
540 uint16_t average_gfx_activity;
541 uint16_t average_umc_activity; // memory controller
542 uint16_t average_mm_activity; // UVD or VCN
543
544 /* Power/Energy */
545 uint16_t average_socket_power;
546 uint32_t energy_accumulator;
547
548 /* Average clocks */
549 uint16_t average_gfxclk_frequency;
550 uint16_t average_socclk_frequency;
551 uint16_t average_uclk_frequency;
552 uint16_t average_vclk0_frequency;
553 uint16_t average_dclk0_frequency;
554 uint16_t average_vclk1_frequency;
555 uint16_t average_dclk1_frequency;
556
557 /* Current clocks */
558 uint16_t current_gfxclk;
559 uint16_t current_socclk;
560 uint16_t current_uclk;
561 uint16_t current_vclk0;
562 uint16_t current_dclk0;
563 uint16_t current_vclk1;
564 uint16_t current_dclk1;
565
566 /* Throttle status */
567 uint32_t throttle_status;
568
569 /* Fans */
570 uint16_t current_fan_speed;
571
572 /* Link width/speed */
573 uint8_t pcie_link_width;
574 uint8_t pcie_link_speed; // in 0.1 GT/s
575};
576
577struct gpu_metrics_v1_1 {
578 struct metrics_table_header common_header;
579
580 /* Temperature */
581 uint16_t temperature_edge;
582 uint16_t temperature_hotspot;
583 uint16_t temperature_mem;
584 uint16_t temperature_vrgfx;
585 uint16_t temperature_vrsoc;
586 uint16_t temperature_vrmem;
587
588 /* Utilization */
589 uint16_t average_gfx_activity;
590 uint16_t average_umc_activity; // memory controller
591 uint16_t average_mm_activity; // UVD or VCN
592
593 /* Power/Energy */
594 uint16_t average_socket_power;
595 uint64_t energy_accumulator;
596
597 /* Driver attached timestamp (in ns) */
598 uint64_t system_clock_counter;
599
600 /* Average clocks */
601 uint16_t average_gfxclk_frequency;
602 uint16_t average_socclk_frequency;
603 uint16_t average_uclk_frequency;
604 uint16_t average_vclk0_frequency;
605 uint16_t average_dclk0_frequency;
606 uint16_t average_vclk1_frequency;
607 uint16_t average_dclk1_frequency;
608
609 /* Current clocks */
610 uint16_t current_gfxclk;
611 uint16_t current_socclk;
612 uint16_t current_uclk;
613 uint16_t current_vclk0;
614 uint16_t current_dclk0;
615 uint16_t current_vclk1;
616 uint16_t current_dclk1;
617
618 /* Throttle status */
619 uint32_t throttle_status;
620
621 /* Fans */
622 uint16_t current_fan_speed;
623
624 /* Link width/speed */
625 uint16_t pcie_link_width;
626 uint16_t pcie_link_speed; // in 0.1 GT/s
627
628 uint16_t padding;
629
630 uint32_t gfx_activity_acc;
631 uint32_t mem_activity_acc;
632
633 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
634};
635
636struct gpu_metrics_v1_2 {
637 struct metrics_table_header common_header;
638
639 /* Temperature */
640 uint16_t temperature_edge;
641 uint16_t temperature_hotspot;
642 uint16_t temperature_mem;
643 uint16_t temperature_vrgfx;
644 uint16_t temperature_vrsoc;
645 uint16_t temperature_vrmem;
646
647 /* Utilization */
648 uint16_t average_gfx_activity;
649 uint16_t average_umc_activity; // memory controller
650 uint16_t average_mm_activity; // UVD or VCN
651
652 /* Power/Energy */
653 uint16_t average_socket_power;
654 uint64_t energy_accumulator;
655
656 /* Driver attached timestamp (in ns) */
657 uint64_t system_clock_counter;
658
659 /* Average clocks */
660 uint16_t average_gfxclk_frequency;
661 uint16_t average_socclk_frequency;
662 uint16_t average_uclk_frequency;
663 uint16_t average_vclk0_frequency;
664 uint16_t average_dclk0_frequency;
665 uint16_t average_vclk1_frequency;
666 uint16_t average_dclk1_frequency;
667
668 /* Current clocks */
669 uint16_t current_gfxclk;
670 uint16_t current_socclk;
671 uint16_t current_uclk;
672 uint16_t current_vclk0;
673 uint16_t current_dclk0;
674 uint16_t current_vclk1;
675 uint16_t current_dclk1;
676
677 /* Throttle status (ASIC dependent) */
678 uint32_t throttle_status;
679
680 /* Fans */
681 uint16_t current_fan_speed;
682
683 /* Link width/speed */
684 uint16_t pcie_link_width;
685 uint16_t pcie_link_speed; // in 0.1 GT/s
686
687 uint16_t padding;
688
689 uint32_t gfx_activity_acc;
690 uint32_t mem_activity_acc;
691
692 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
693
694 /* PMFW attached timestamp (10ns resolution) */
695 uint64_t firmware_timestamp;
696};
697
698struct gpu_metrics_v1_3 {
699 struct metrics_table_header common_header;
700
701 /* Temperature */
702 uint16_t temperature_edge;
703 uint16_t temperature_hotspot;
704 uint16_t temperature_mem;
705 uint16_t temperature_vrgfx;
706 uint16_t temperature_vrsoc;
707 uint16_t temperature_vrmem;
708
709 /* Utilization */
710 uint16_t average_gfx_activity;
711 uint16_t average_umc_activity; // memory controller
712 uint16_t average_mm_activity; // UVD or VCN
713
714 /* Power/Energy */
715 uint16_t average_socket_power;
716 uint64_t energy_accumulator;
717
718 /* Driver attached timestamp (in ns) */
719 uint64_t system_clock_counter;
720
721 /* Average clocks */
722 uint16_t average_gfxclk_frequency;
723 uint16_t average_socclk_frequency;
724 uint16_t average_uclk_frequency;
725 uint16_t average_vclk0_frequency;
726 uint16_t average_dclk0_frequency;
727 uint16_t average_vclk1_frequency;
728 uint16_t average_dclk1_frequency;
729
730 /* Current clocks */
731 uint16_t current_gfxclk;
732 uint16_t current_socclk;
733 uint16_t current_uclk;
734 uint16_t current_vclk0;
735 uint16_t current_dclk0;
736 uint16_t current_vclk1;
737 uint16_t current_dclk1;
738
739 /* Throttle status */
740 uint32_t throttle_status;
741
742 /* Fans */
743 uint16_t current_fan_speed;
744
745 /* Link width/speed */
746 uint16_t pcie_link_width;
747 uint16_t pcie_link_speed; // in 0.1 GT/s
748
749 uint16_t padding;
750
751 uint32_t gfx_activity_acc;
752 uint32_t mem_activity_acc;
753
754 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
755
756 /* PMFW attached timestamp (10ns resolution) */
757 uint64_t firmware_timestamp;
758
759 /* Voltage (mV) */
760 uint16_t voltage_soc;
761 uint16_t voltage_gfx;
762 uint16_t voltage_mem;
763
764 uint16_t padding1;
765
766 /* Throttle status (ASIC independent) */
767 uint64_t indep_throttle_status;
768};
769
770struct gpu_metrics_v1_4 {
771 struct metrics_table_header common_header;
772
773 /* Temperature (Celsius) */
774 uint16_t temperature_hotspot;
775 uint16_t temperature_mem;
776 uint16_t temperature_vrsoc;
777
778 /* Power (Watts) */
779 uint16_t curr_socket_power;
780
781 /* Utilization (%) */
782 uint16_t average_gfx_activity;
783 uint16_t average_umc_activity; // memory controller
784 uint16_t vcn_activity[NUM_VCN];
785
786 /* Energy (15.259uJ (2^-16) units) */
787 uint64_t energy_accumulator;
788
789 /* Driver attached timestamp (in ns) */
790 uint64_t system_clock_counter;
791
792 /* Throttle status */
793 uint32_t throttle_status;
794
795 /* Clock Lock Status. Each bit corresponds to clock instance */
796 uint32_t gfxclk_lock_status;
797
798 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
799 uint16_t pcie_link_width;
800 uint16_t pcie_link_speed;
801
802 /* XGMI bus width and bitrate (in Gbps) */
803 uint16_t xgmi_link_width;
804 uint16_t xgmi_link_speed;
805
806 /* Utilization Accumulated (%) */
807 uint32_t gfx_activity_acc;
808 uint32_t mem_activity_acc;
809
810 /*PCIE accumulated bandwidth (GB/sec) */
811 uint64_t pcie_bandwidth_acc;
812
813 /*PCIE instantaneous bandwidth (GB/sec) */
814 uint64_t pcie_bandwidth_inst;
815
816 /* PCIE L0 to recovery state transition accumulated count */
817 uint64_t pcie_l0_to_recov_count_acc;
818
819 /* PCIE replay accumulated count */
820 uint64_t pcie_replay_count_acc;
821
822 /* PCIE replay rollover accumulated count */
823 uint64_t pcie_replay_rover_count_acc;
824
825 /* XGMI accumulated data transfer size(KiloBytes) */
826 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
827 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
828
829 /* PMFW attached timestamp (10ns resolution) */
830 uint64_t firmware_timestamp;
831
832 /* Current clocks (Mhz) */
833 uint16_t current_gfxclk[MAX_GFX_CLKS];
834 uint16_t current_socclk[MAX_CLKS];
835 uint16_t current_vclk0[MAX_CLKS];
836 uint16_t current_dclk0[MAX_CLKS];
837 uint16_t current_uclk;
838
839 uint16_t padding;
840};
841
842struct gpu_metrics_v1_5 {
843 struct metrics_table_header common_header;
844
845 /* Temperature (Celsius) */
846 uint16_t temperature_hotspot;
847 uint16_t temperature_mem;
848 uint16_t temperature_vrsoc;
849
850 /* Power (Watts) */
851 uint16_t curr_socket_power;
852
853 /* Utilization (%) */
854 uint16_t average_gfx_activity;
855 uint16_t average_umc_activity; // memory controller
856 uint16_t vcn_activity[NUM_VCN];
857 uint16_t jpeg_activity[NUM_JPEG_ENG];
858
859 /* Energy (15.259uJ (2^-16) units) */
860 uint64_t energy_accumulator;
861
862 /* Driver attached timestamp (in ns) */
863 uint64_t system_clock_counter;
864
865 /* Throttle status */
866 uint32_t throttle_status;
867
868 /* Clock Lock Status. Each bit corresponds to clock instance */
869 uint32_t gfxclk_lock_status;
870
871 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
872 uint16_t pcie_link_width;
873 uint16_t pcie_link_speed;
874
875 /* XGMI bus width and bitrate (in Gbps) */
876 uint16_t xgmi_link_width;
877 uint16_t xgmi_link_speed;
878
879 /* Utilization Accumulated (%) */
880 uint32_t gfx_activity_acc;
881 uint32_t mem_activity_acc;
882
883 /*PCIE accumulated bandwidth (GB/sec) */
884 uint64_t pcie_bandwidth_acc;
885
886 /*PCIE instantaneous bandwidth (GB/sec) */
887 uint64_t pcie_bandwidth_inst;
888
889 /* PCIE L0 to recovery state transition accumulated count */
890 uint64_t pcie_l0_to_recov_count_acc;
891
892 /* PCIE replay accumulated count */
893 uint64_t pcie_replay_count_acc;
894
895 /* PCIE replay rollover accumulated count */
896 uint64_t pcie_replay_rover_count_acc;
897
898 /* PCIE NAK sent accumulated count */
899 uint32_t pcie_nak_sent_count_acc;
900
901 /* PCIE NAK received accumulated count */
902 uint32_t pcie_nak_rcvd_count_acc;
903
904 /* XGMI accumulated data transfer size(KiloBytes) */
905 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
906 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
907
908 /* PMFW attached timestamp (10ns resolution) */
909 uint64_t firmware_timestamp;
910
911 /* Current clocks (Mhz) */
912 uint16_t current_gfxclk[MAX_GFX_CLKS];
913 uint16_t current_socclk[MAX_CLKS];
914 uint16_t current_vclk0[MAX_CLKS];
915 uint16_t current_dclk0[MAX_CLKS];
916 uint16_t current_uclk;
917
918 uint16_t padding;
919};
920
921struct gpu_metrics_v1_6 {
922 struct metrics_table_header common_header;
923
924 /* Temperature (Celsius) */
925 uint16_t temperature_hotspot;
926 uint16_t temperature_mem;
927 uint16_t temperature_vrsoc;
928
929 /* Power (Watts) */
930 uint16_t curr_socket_power;
931
932 /* Utilization (%) */
933 uint16_t average_gfx_activity;
934 uint16_t average_umc_activity; // memory controller
935
936 /* Energy (15.259uJ (2^-16) units) */
937 uint64_t energy_accumulator;
938
939 /* Driver attached timestamp (in ns) */
940 uint64_t system_clock_counter;
941
942 /* Accumulation cycle counter */
943 uint32_t accumulation_counter;
944
945 /* Accumulated throttler residencies */
946 uint32_t prochot_residency_acc;
947 uint32_t ppt_residency_acc;
948 uint32_t socket_thm_residency_acc;
949 uint32_t vr_thm_residency_acc;
950 uint32_t hbm_thm_residency_acc;
951
952 /* Clock Lock Status. Each bit corresponds to clock instance */
953 uint32_t gfxclk_lock_status;
954
955 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
956 uint16_t pcie_link_width;
957 uint16_t pcie_link_speed;
958
959 /* XGMI bus width and bitrate (in Gbps) */
960 uint16_t xgmi_link_width;
961 uint16_t xgmi_link_speed;
962
963 /* Utilization Accumulated (%) */
964 uint32_t gfx_activity_acc;
965 uint32_t mem_activity_acc;
966
967 /*PCIE accumulated bandwidth (GB/sec) */
968 uint64_t pcie_bandwidth_acc;
969
970 /*PCIE instantaneous bandwidth (GB/sec) */
971 uint64_t pcie_bandwidth_inst;
972
973 /* PCIE L0 to recovery state transition accumulated count */
974 uint64_t pcie_l0_to_recov_count_acc;
975
976 /* PCIE replay accumulated count */
977 uint64_t pcie_replay_count_acc;
978
979 /* PCIE replay rollover accumulated count */
980 uint64_t pcie_replay_rover_count_acc;
981
982 /* PCIE NAK sent accumulated count */
983 uint32_t pcie_nak_sent_count_acc;
984
985 /* PCIE NAK received accumulated count */
986 uint32_t pcie_nak_rcvd_count_acc;
987
988 /* XGMI accumulated data transfer size(KiloBytes) */
989 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
990 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
991
992 /* PMFW attached timestamp (10ns resolution) */
993 uint64_t firmware_timestamp;
994
995 /* Current clocks (Mhz) */
996 uint16_t current_gfxclk[MAX_GFX_CLKS];
997 uint16_t current_socclk[MAX_CLKS];
998 uint16_t current_vclk0[MAX_CLKS];
999 uint16_t current_dclk0[MAX_CLKS];
1000 uint16_t current_uclk;
1001
1002 /* Number of current partition */
1003 uint16_t num_partition;
1004
1005 /* XCP metrics stats */
1006 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP];
1007
1008 /* PCIE other end recovery counter */
1009 uint32_t pcie_lc_perf_other_end_recovery;
1010};
1011
1012struct gpu_metrics_v1_7 {
1013 struct metrics_table_header common_header;
1014
1015 /* Temperature (Celsius) */
1016 uint16_t temperature_hotspot;
1017 uint16_t temperature_mem;
1018 uint16_t temperature_vrsoc;
1019
1020 /* Power (Watts) */
1021 uint16_t curr_socket_power;
1022
1023 /* Utilization (%) */
1024 uint16_t average_gfx_activity;
1025 uint16_t average_umc_activity; // memory controller
1026
1027 /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1028 uint64_t mem_max_bandwidth;
1029
1030 /* Energy (15.259uJ (2^-16) units) */
1031 uint64_t energy_accumulator;
1032
1033 /* Driver attached timestamp (in ns) */
1034 uint64_t system_clock_counter;
1035
1036 /* Accumulation cycle counter */
1037 uint32_t accumulation_counter;
1038
1039 /* Accumulated throttler residencies */
1040 uint32_t prochot_residency_acc;
1041 uint32_t ppt_residency_acc;
1042 uint32_t socket_thm_residency_acc;
1043 uint32_t vr_thm_residency_acc;
1044 uint32_t hbm_thm_residency_acc;
1045
1046 /* Clock Lock Status. Each bit corresponds to clock instance */
1047 uint32_t gfxclk_lock_status;
1048
1049 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1050 uint16_t pcie_link_width;
1051 uint16_t pcie_link_speed;
1052
1053 /* XGMI bus width and bitrate (in Gbps) */
1054 uint16_t xgmi_link_width;
1055 uint16_t xgmi_link_speed;
1056
1057 /* Utilization Accumulated (%) */
1058 uint32_t gfx_activity_acc;
1059 uint32_t mem_activity_acc;
1060
1061 /*PCIE accumulated bandwidth (GB/sec) */
1062 uint64_t pcie_bandwidth_acc;
1063
1064 /*PCIE instantaneous bandwidth (GB/sec) */
1065 uint64_t pcie_bandwidth_inst;
1066
1067 /* PCIE L0 to recovery state transition accumulated count */
1068 uint64_t pcie_l0_to_recov_count_acc;
1069
1070 /* PCIE replay accumulated count */
1071 uint64_t pcie_replay_count_acc;
1072
1073 /* PCIE replay rollover accumulated count */
1074 uint64_t pcie_replay_rover_count_acc;
1075
1076 /* PCIE NAK sent accumulated count */
1077 uint32_t pcie_nak_sent_count_acc;
1078
1079 /* PCIE NAK received accumulated count */
1080 uint32_t pcie_nak_rcvd_count_acc;
1081
1082 /* XGMI accumulated data transfer size(KiloBytes) */
1083 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1084 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1085
1086 /* XGMI link status(active/inactive) */
1087 uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1088
1089 uint16_t padding;
1090
1091 /* PMFW attached timestamp (10ns resolution) */
1092 uint64_t firmware_timestamp;
1093
1094 /* Current clocks (Mhz) */
1095 uint16_t current_gfxclk[MAX_GFX_CLKS];
1096 uint16_t current_socclk[MAX_CLKS];
1097 uint16_t current_vclk0[MAX_CLKS];
1098 uint16_t current_dclk0[MAX_CLKS];
1099 uint16_t current_uclk;
1100
1101 /* Number of current partition */
1102 uint16_t num_partition;
1103
1104 /* XCP metrics stats */
1105 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP];
1106
1107 /* PCIE other end recovery counter */
1108 uint32_t pcie_lc_perf_other_end_recovery;
1109};
1110
1111struct gpu_metrics_v1_8 {
1112 struct metrics_table_header common_header;
1113
1114 /* Temperature (Celsius) */
1115 uint16_t temperature_hotspot;
1116 uint16_t temperature_mem;
1117 uint16_t temperature_vrsoc;
1118
1119 /* Power (Watts) */
1120 uint16_t curr_socket_power;
1121
1122 /* Utilization (%) */
1123 uint16_t average_gfx_activity;
1124 uint16_t average_umc_activity; // memory controller
1125
1126 /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1127 uint64_t mem_max_bandwidth;
1128
1129 /* Energy (15.259uJ (2^-16) units) */
1130 uint64_t energy_accumulator;
1131
1132 /* Driver attached timestamp (in ns) */
1133 uint64_t system_clock_counter;
1134
1135 /* Accumulation cycle counter */
1136 uint32_t accumulation_counter;
1137
1138 /* Accumulated throttler residencies */
1139 uint32_t prochot_residency_acc;
1140 uint32_t ppt_residency_acc;
1141 uint32_t socket_thm_residency_acc;
1142 uint32_t vr_thm_residency_acc;
1143 uint32_t hbm_thm_residency_acc;
1144
1145 /* Clock Lock Status. Each bit corresponds to clock instance */
1146 uint32_t gfxclk_lock_status;
1147
1148 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1149 uint16_t pcie_link_width;
1150 uint16_t pcie_link_speed;
1151
1152 /* XGMI bus width and bitrate (in Gbps) */
1153 uint16_t xgmi_link_width;
1154 uint16_t xgmi_link_speed;
1155
1156 /* Utilization Accumulated (%) */
1157 uint32_t gfx_activity_acc;
1158 uint32_t mem_activity_acc;
1159
1160 /*PCIE accumulated bandwidth (GB/sec) */
1161 uint64_t pcie_bandwidth_acc;
1162
1163 /*PCIE instantaneous bandwidth (GB/sec) */
1164 uint64_t pcie_bandwidth_inst;
1165
1166 /* PCIE L0 to recovery state transition accumulated count */
1167 uint64_t pcie_l0_to_recov_count_acc;
1168
1169 /* PCIE replay accumulated count */
1170 uint64_t pcie_replay_count_acc;
1171
1172 /* PCIE replay rollover accumulated count */
1173 uint64_t pcie_replay_rover_count_acc;
1174
1175 /* PCIE NAK sent accumulated count */
1176 uint32_t pcie_nak_sent_count_acc;
1177
1178 /* PCIE NAK received accumulated count */
1179 uint32_t pcie_nak_rcvd_count_acc;
1180
1181 /* XGMI accumulated data transfer size(KiloBytes) */
1182 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1183 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1184
1185 /* XGMI link status(active/inactive) */
1186 uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1187
1188 uint16_t padding;
1189
1190 /* PMFW attached timestamp (10ns resolution) */
1191 uint64_t firmware_timestamp;
1192
1193 /* Current clocks (Mhz) */
1194 uint16_t current_gfxclk[MAX_GFX_CLKS];
1195 uint16_t current_socclk[MAX_CLKS];
1196 uint16_t current_vclk0[MAX_CLKS];
1197 uint16_t current_dclk0[MAX_CLKS];
1198 uint16_t current_uclk;
1199
1200 /* Number of current partition */
1201 uint16_t num_partition;
1202
1203 /* XCP metrics stats */
1204 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP];
1205
1206 /* PCIE other end recovery counter */
1207 uint32_t pcie_lc_perf_other_end_recovery;
1208};
1209
1210/*
1211 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1212 * Use gpu_metrics_v2_1 or later instead.
1213 */
1214struct gpu_metrics_v2_0 {
1215 struct metrics_table_header common_header;
1216
1217 /* Driver attached timestamp (in ns) */
1218 uint64_t system_clock_counter;
1219
1220 /* Temperature */
1221 uint16_t temperature_gfx; // gfx temperature on APUs
1222 uint16_t temperature_soc; // soc temperature on APUs
1223 uint16_t temperature_core[8]; // CPU core temperature on APUs
1224 uint16_t temperature_l3[2];
1225
1226 /* Utilization */
1227 uint16_t average_gfx_activity;
1228 uint16_t average_mm_activity; // UVD or VCN
1229
1230 /* Power/Energy */
1231 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1232 uint16_t average_cpu_power;
1233 uint16_t average_soc_power;
1234 uint16_t average_gfx_power;
1235 uint16_t average_core_power[8]; // CPU core power on APUs
1236
1237 /* Average clocks */
1238 uint16_t average_gfxclk_frequency;
1239 uint16_t average_socclk_frequency;
1240 uint16_t average_uclk_frequency;
1241 uint16_t average_fclk_frequency;
1242 uint16_t average_vclk_frequency;
1243 uint16_t average_dclk_frequency;
1244
1245 /* Current clocks */
1246 uint16_t current_gfxclk;
1247 uint16_t current_socclk;
1248 uint16_t current_uclk;
1249 uint16_t current_fclk;
1250 uint16_t current_vclk;
1251 uint16_t current_dclk;
1252 uint16_t current_coreclk[8]; // CPU core clocks
1253 uint16_t current_l3clk[2];
1254
1255 /* Throttle status */
1256 uint32_t throttle_status;
1257
1258 /* Fans */
1259 uint16_t fan_pwm;
1260
1261 uint16_t padding;
1262};
1263
1264struct gpu_metrics_v2_1 {
1265 struct metrics_table_header common_header;
1266
1267 /* Temperature */
1268 uint16_t temperature_gfx; // gfx temperature on APUs
1269 uint16_t temperature_soc; // soc temperature on APUs
1270 uint16_t temperature_core[8]; // CPU core temperature on APUs
1271 uint16_t temperature_l3[2];
1272
1273 /* Utilization */
1274 uint16_t average_gfx_activity;
1275 uint16_t average_mm_activity; // UVD or VCN
1276
1277 /* Driver attached timestamp (in ns) */
1278 uint64_t system_clock_counter;
1279
1280 /* Power/Energy */
1281 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1282 uint16_t average_cpu_power;
1283 uint16_t average_soc_power;
1284 uint16_t average_gfx_power;
1285 uint16_t average_core_power[8]; // CPU core power on APUs
1286
1287 /* Average clocks */
1288 uint16_t average_gfxclk_frequency;
1289 uint16_t average_socclk_frequency;
1290 uint16_t average_uclk_frequency;
1291 uint16_t average_fclk_frequency;
1292 uint16_t average_vclk_frequency;
1293 uint16_t average_dclk_frequency;
1294
1295 /* Current clocks */
1296 uint16_t current_gfxclk;
1297 uint16_t current_socclk;
1298 uint16_t current_uclk;
1299 uint16_t current_fclk;
1300 uint16_t current_vclk;
1301 uint16_t current_dclk;
1302 uint16_t current_coreclk[8]; // CPU core clocks
1303 uint16_t current_l3clk[2];
1304
1305 /* Throttle status */
1306 uint32_t throttle_status;
1307
1308 /* Fans */
1309 uint16_t fan_pwm;
1310
1311 uint16_t padding[3];
1312};
1313
1314struct gpu_metrics_v2_2 {
1315 struct metrics_table_header common_header;
1316
1317 /* Temperature */
1318 uint16_t temperature_gfx; // gfx temperature on APUs
1319 uint16_t temperature_soc; // soc temperature on APUs
1320 uint16_t temperature_core[8]; // CPU core temperature on APUs
1321 uint16_t temperature_l3[2];
1322
1323 /* Utilization */
1324 uint16_t average_gfx_activity;
1325 uint16_t average_mm_activity; // UVD or VCN
1326
1327 /* Driver attached timestamp (in ns) */
1328 uint64_t system_clock_counter;
1329
1330 /* Power/Energy */
1331 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1332 uint16_t average_cpu_power;
1333 uint16_t average_soc_power;
1334 uint16_t average_gfx_power;
1335 uint16_t average_core_power[8]; // CPU core power on APUs
1336
1337 /* Average clocks */
1338 uint16_t average_gfxclk_frequency;
1339 uint16_t average_socclk_frequency;
1340 uint16_t average_uclk_frequency;
1341 uint16_t average_fclk_frequency;
1342 uint16_t average_vclk_frequency;
1343 uint16_t average_dclk_frequency;
1344
1345 /* Current clocks */
1346 uint16_t current_gfxclk;
1347 uint16_t current_socclk;
1348 uint16_t current_uclk;
1349 uint16_t current_fclk;
1350 uint16_t current_vclk;
1351 uint16_t current_dclk;
1352 uint16_t current_coreclk[8]; // CPU core clocks
1353 uint16_t current_l3clk[2];
1354
1355 /* Throttle status (ASIC dependent) */
1356 uint32_t throttle_status;
1357
1358 /* Fans */
1359 uint16_t fan_pwm;
1360
1361 uint16_t padding[3];
1362
1363 /* Throttle status (ASIC independent) */
1364 uint64_t indep_throttle_status;
1365};
1366
1367struct gpu_metrics_v2_3 {
1368 struct metrics_table_header common_header;
1369
1370 /* Temperature */
1371 uint16_t temperature_gfx; // gfx temperature on APUs
1372 uint16_t temperature_soc; // soc temperature on APUs
1373 uint16_t temperature_core[8]; // CPU core temperature on APUs
1374 uint16_t temperature_l3[2];
1375
1376 /* Utilization */
1377 uint16_t average_gfx_activity;
1378 uint16_t average_mm_activity; // UVD or VCN
1379
1380 /* Driver attached timestamp (in ns) */
1381 uint64_t system_clock_counter;
1382
1383 /* Power/Energy */
1384 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1385 uint16_t average_cpu_power;
1386 uint16_t average_soc_power;
1387 uint16_t average_gfx_power;
1388 uint16_t average_core_power[8]; // CPU core power on APUs
1389
1390 /* Average clocks */
1391 uint16_t average_gfxclk_frequency;
1392 uint16_t average_socclk_frequency;
1393 uint16_t average_uclk_frequency;
1394 uint16_t average_fclk_frequency;
1395 uint16_t average_vclk_frequency;
1396 uint16_t average_dclk_frequency;
1397
1398 /* Current clocks */
1399 uint16_t current_gfxclk;
1400 uint16_t current_socclk;
1401 uint16_t current_uclk;
1402 uint16_t current_fclk;
1403 uint16_t current_vclk;
1404 uint16_t current_dclk;
1405 uint16_t current_coreclk[8]; // CPU core clocks
1406 uint16_t current_l3clk[2];
1407
1408 /* Throttle status (ASIC dependent) */
1409 uint32_t throttle_status;
1410
1411 /* Fans */
1412 uint16_t fan_pwm;
1413
1414 uint16_t padding[3];
1415
1416 /* Throttle status (ASIC independent) */
1417 uint64_t indep_throttle_status;
1418
1419 /* Average Temperature */
1420 uint16_t average_temperature_gfx; // average gfx temperature on APUs
1421 uint16_t average_temperature_soc; // average soc temperature on APUs
1422 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs
1423 uint16_t average_temperature_l3[2];
1424};
1425
1426struct gpu_metrics_v2_4 {
1427 struct metrics_table_header common_header;
1428
1429 /* Temperature (unit: centi-Celsius) */
1430 uint16_t temperature_gfx;
1431 uint16_t temperature_soc;
1432 uint16_t temperature_core[8];
1433 uint16_t temperature_l3[2];
1434
1435 /* Utilization (unit: centi) */
1436 uint16_t average_gfx_activity;
1437 uint16_t average_mm_activity;
1438
1439 /* Driver attached timestamp (in ns) */
1440 uint64_t system_clock_counter;
1441
1442 /* Power/Energy (unit: mW) */
1443 uint16_t average_socket_power;
1444 uint16_t average_cpu_power;
1445 uint16_t average_soc_power;
1446 uint16_t average_gfx_power;
1447 uint16_t average_core_power[8];
1448
1449 /* Average clocks (unit: MHz) */
1450 uint16_t average_gfxclk_frequency;
1451 uint16_t average_socclk_frequency;
1452 uint16_t average_uclk_frequency;
1453 uint16_t average_fclk_frequency;
1454 uint16_t average_vclk_frequency;
1455 uint16_t average_dclk_frequency;
1456
1457 /* Current clocks (unit: MHz) */
1458 uint16_t current_gfxclk;
1459 uint16_t current_socclk;
1460 uint16_t current_uclk;
1461 uint16_t current_fclk;
1462 uint16_t current_vclk;
1463 uint16_t current_dclk;
1464 uint16_t current_coreclk[8];
1465 uint16_t current_l3clk[2];
1466
1467 /* Throttle status (ASIC dependent) */
1468 uint32_t throttle_status;
1469
1470 /* Fans */
1471 uint16_t fan_pwm;
1472
1473 uint16_t padding[3];
1474
1475 /* Throttle status (ASIC independent) */
1476 uint64_t indep_throttle_status;
1477
1478 /* Average Temperature (unit: centi-Celsius) */
1479 uint16_t average_temperature_gfx;
1480 uint16_t average_temperature_soc;
1481 uint16_t average_temperature_core[8];
1482 uint16_t average_temperature_l3[2];
1483
1484 /* Power/Voltage (unit: mV) */
1485 uint16_t average_cpu_voltage;
1486 uint16_t average_soc_voltage;
1487 uint16_t average_gfx_voltage;
1488
1489 /* Power/Current (unit: mA) */
1490 uint16_t average_cpu_current;
1491 uint16_t average_soc_current;
1492 uint16_t average_gfx_current;
1493};
1494
1495struct gpu_metrics_v3_0 {
1496 struct metrics_table_header common_header;
1497
1498 /* Temperature */
1499 /* gfx temperature on APUs */
1500 uint16_t temperature_gfx;
1501 /* soc temperature on APUs */
1502 uint16_t temperature_soc;
1503 /* CPU core temperature on APUs */
1504 uint16_t temperature_core[16];
1505 /* skin temperature on APUs */
1506 uint16_t temperature_skin;
1507
1508 /* Utilization */
1509 /* time filtered GFX busy % [0-100] */
1510 uint16_t average_gfx_activity;
1511 /* time filtered VCN busy % [0-100] */
1512 uint16_t average_vcn_activity;
1513 /* time filtered IPU per-column busy % [0-100] */
1514 uint16_t average_ipu_activity[8];
1515 /* time filtered per-core C0 residency % [0-100]*/
1516 uint16_t average_core_c0_activity[16];
1517 /* time filtered DRAM read bandwidth [MB/sec] */
1518 uint16_t average_dram_reads;
1519 /* time filtered DRAM write bandwidth [MB/sec] */
1520 uint16_t average_dram_writes;
1521 /* time filtered IPU read bandwidth [MB/sec] */
1522 uint16_t average_ipu_reads;
1523 /* time filtered IPU write bandwidth [MB/sec] */
1524 uint16_t average_ipu_writes;
1525
1526 /* Driver attached timestamp (in ns) */
1527 uint64_t system_clock_counter;
1528
1529 /* Power/Energy */
1530 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1531 uint32_t average_socket_power;
1532 /* time filtered IPU power [mW] */
1533 uint16_t average_ipu_power;
1534 /* time filtered APU power [mW] */
1535 uint32_t average_apu_power;
1536 /* time filtered GFX power [mW] */
1537 uint32_t average_gfx_power;
1538 /* time filtered dGPU power [mW] */
1539 uint32_t average_dgpu_power;
1540 /* time filtered sum of core power across all cores in the socket [mW] */
1541 uint32_t average_all_core_power;
1542 /* calculated core power [mW] */
1543 uint16_t average_core_power[16];
1544 /* time filtered total system power [mW] */
1545 uint16_t average_sys_power;
1546 /* maximum IRM defined STAPM power limit [mW] */
1547 uint16_t stapm_power_limit;
1548 /* time filtered STAPM power limit [mW] */
1549 uint16_t current_stapm_power_limit;
1550
1551 /* time filtered clocks [MHz] */
1552 uint16_t average_gfxclk_frequency;
1553 uint16_t average_socclk_frequency;
1554 uint16_t average_vpeclk_frequency;
1555 uint16_t average_ipuclk_frequency;
1556 uint16_t average_fclk_frequency;
1557 uint16_t average_vclk_frequency;
1558 uint16_t average_uclk_frequency;
1559 uint16_t average_mpipu_frequency;
1560
1561 /* Current clocks */
1562 /* target core frequency [MHz] */
1563 uint16_t current_coreclk[16];
1564 /* CCLK frequency limit enforced on classic cores [MHz] */
1565 uint16_t current_core_maxfreq;
1566 /* GFXCLK frequency limit enforced on GFX [MHz] */
1567 uint16_t current_gfx_maxfreq;
1568
1569 /* Throttle Residency (ASIC dependent) */
1570 uint32_t throttle_residency_prochot;
1571 uint32_t throttle_residency_spl;
1572 uint32_t throttle_residency_fppt;
1573 uint32_t throttle_residency_sppt;
1574 uint32_t throttle_residency_thm_core;
1575 uint32_t throttle_residency_thm_gfx;
1576 uint32_t throttle_residency_thm_soc;
1577
1578 /* Metrics table alpha filter time constant [us] */
1579 uint32_t time_filter_alphavalue;
1580};
1581
1582struct amdgpu_pmmetrics_header {
1583 uint16_t structure_size;
1584 uint16_t pad;
1585 uint32_t mp1_ip_discovery_version;
1586 uint32_t pmfw_version;
1587 uint32_t pmmetrics_version;
1588};
1589
1590struct amdgpu_pm_metrics {
1591 struct amdgpu_pmmetrics_header common_header;
1592
1593 uint8_t data[];
1594};
1595
1596struct amdgpu_partition_metrics_v1_0 {
1597 struct metrics_table_header common_header;
1598 /* Current clocks (Mhz) */
1599 uint16_t current_gfxclk[MAX_XCC];
1600 uint16_t current_socclk[MAX_CLKS];
1601 uint16_t current_vclk0[MAX_CLKS];
1602 uint16_t current_dclk0[MAX_CLKS];
1603 uint16_t current_uclk;
1604 uint16_t padding;
1605
1606 /* Utilization Instantaneous (%) */
1607 uint32_t gfx_busy_inst[MAX_XCC];
1608 uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
1609 uint16_t vcn_busy[NUM_VCN];
1610 /* Utilization Accumulated (%) */
1611 uint64_t gfx_busy_acc[MAX_XCC];
1612 /* Total App Clock Counter Accumulated */
1613 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
1614 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
1615 uint64_t gfx_low_utilization_acc[MAX_XCC];
1616 uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
1617};
1618
1619#endif