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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef AMDGPU_USERQ_H_
26#define AMDGPU_USERQ_H_
27#include "amdgpu_eviction_fence.h"
28
29#define AMDGPU_MAX_USERQ_COUNT 512
30
31#define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base)
32#define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr)
33#define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name)
34
35enum amdgpu_userq_state {
36 AMDGPU_USERQ_STATE_UNMAPPED = 0,
37 AMDGPU_USERQ_STATE_MAPPED,
38 AMDGPU_USERQ_STATE_PREEMPTED,
39 AMDGPU_USERQ_STATE_HUNG,
40};
41
42struct amdgpu_mqd_prop;
43
44struct amdgpu_userq_obj {
45 void *cpu_ptr;
46 uint64_t gpu_addr;
47 struct amdgpu_bo *obj;
48};
49
50struct amdgpu_usermode_queue {
51 int queue_type;
52 enum amdgpu_userq_state state;
53 uint64_t doorbell_handle;
54 uint64_t doorbell_index;
55 uint64_t flags;
56 struct amdgpu_mqd_prop *userq_prop;
57 struct amdgpu_userq_mgr *userq_mgr;
58 struct amdgpu_vm *vm;
59 struct amdgpu_userq_obj mqd;
60 struct amdgpu_userq_obj db_obj;
61 struct amdgpu_userq_obj fw_obj;
62 struct amdgpu_userq_obj wptr_obj;
63 struct xarray fence_drv_xa;
64 struct amdgpu_userq_fence_driver *fence_drv;
65 struct dma_fence *last_fence;
66 u32 xcp_id;
67 int priority;
68};
69
70struct amdgpu_userq_funcs {
71 int (*mqd_create)(struct amdgpu_userq_mgr *uq_mgr,
72 struct drm_amdgpu_userq_in *args,
73 struct amdgpu_usermode_queue *queue);
74 void (*mqd_destroy)(struct amdgpu_userq_mgr *uq_mgr,
75 struct amdgpu_usermode_queue *uq);
76 int (*unmap)(struct amdgpu_userq_mgr *uq_mgr,
77 struct amdgpu_usermode_queue *queue);
78 int (*map)(struct amdgpu_userq_mgr *uq_mgr,
79 struct amdgpu_usermode_queue *queue);
80};
81
82/* Usermode queues for gfx */
83struct amdgpu_userq_mgr {
84 struct idr userq_idr;
85 struct mutex userq_mutex;
86 struct amdgpu_device *adev;
87 struct delayed_work resume_work;
88 struct list_head list;
89 struct drm_file *file;
90};
91
92struct amdgpu_db_info {
93 uint64_t doorbell_handle;
94 uint32_t queue_type;
95 uint32_t doorbell_offset;
96 struct amdgpu_userq_obj *db_obj;
97};
98
99int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
100
101int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv,
102 struct amdgpu_device *adev);
103
104void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr);
105
106int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr,
107 struct amdgpu_userq_obj *userq_obj,
108 int size);
109
110void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr,
111 struct amdgpu_userq_obj *userq_obj);
112
113void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr,
114 struct amdgpu_eviction_fence *ev_fence);
115
116int amdgpu_userq_active(struct amdgpu_userq_mgr *uq_mgr);
117
118void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr,
119 struct amdgpu_eviction_fence_mgr *evf_mgr);
120
121uint64_t amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,
122 struct amdgpu_db_info *db_info,
123 struct drm_file *filp);
124
125u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev);
126
127int amdgpu_userq_suspend(struct amdgpu_device *adev);
128int amdgpu_userq_resume(struct amdgpu_device *adev);
129
130int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,
131 u32 idx);
132int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev,
133 u32 idx);
134
135#endif