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kernel / Documentation / gpu / amdgpu / display / dc-glossary.rst
at v6.16-rc4 231 lines 3.5 kB view raw
1=========== 2DC Glossary 3=========== 4 5On this page, we try to keep track of acronyms related to the display 6component. If you do not find what you are looking for, look at the 7'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere, 8consider asking in the amdgfx and update this page. 9 10.. glossary:: 11 12 ABM 13 Adaptive Backlight Modulation 14 15 APU 16 Accelerated Processing Unit 17 18 ASIC 19 Application-Specific Integrated Circuit 20 21 ASSR 22 Alternate Scrambler Seed Reset 23 24 AZ 25 Azalia (HD audio DMA engine) 26 27 BPC 28 Bits Per Colour/Component 29 30 BPP 31 Bits Per Pixel 32 33 Clocks 34 * PCLK: Pixel Clock 35 * SYMCLK: Symbol Clock 36 * SOCCLK: GPU Engine Clock 37 * DISPCLK: Display Clock 38 * DPPCLK: DPP Clock 39 * DCFCLK: Display Controller Fabric Clock 40 * REFCLK: Real Time Reference Clock 41 * PPLL: Pixel PLL 42 * FCLK: Fabric Clock 43 * MCLK: Memory Clock 44 45 CRC 46 Cyclic Redundancy Check 47 48 CRTC 49 Cathode Ray Tube Controller - commonly called "Controller" - Generates 50 raw stream of pixels, clocked at pixel clock 51 52 CVT 53 Coordinated Video Timings 54 55 DAL 56 Display Abstraction layer 57 58 DC (Software) 59 Display Core 60 61 DC (Hardware) 62 Display Controller 63 64 DCC 65 Delta Colour Compression 66 67 DCE 68 Display Controller Engine 69 70 DCHUB 71 Display Controller HUB 72 73 ARB 74 Arbiter 75 76 VTG 77 Vertical Timing Generator 78 79 DCN 80 Display Core Next 81 82 DCCG 83 Display Clock Generator block 84 85 DDC 86 Display Data Channel 87 88 DIO 89 Display IO 90 91 DPP 92 Display Pipes and Planes 93 94 DSC 95 Display Stream Compression (Reduce the amount of bits to represent pixel 96 count while at the same pixel clock) 97 98 dGPU 99 discrete GPU 100 101 DMIF 102 Display Memory Interface 103 104 DML 105 Display Mode Library 106 107 DMCU 108 Display Micro-Controller Unit 109 110 DMCUB 111 Display Micro-Controller Unit, version B 112 113 DPCD 114 DisplayPort Configuration Data 115 116 DPM(S) 117 Display Power Management (Signaling) 118 119 DRR 120 Dynamic Refresh Rate 121 122 DWB 123 Display Writeback 124 125 FB 126 Frame Buffer 127 128 FBC 129 Frame Buffer Compression 130 131 FEC 132 Forward Error Correction 133 134 FRL 135 Fixed Rate Link 136 137 GCO 138 Graphical Controller Object 139 140 GSL 141 Global Swap Lock 142 143 iGPU 144 integrated GPU 145 146 ISR 147 Interrupt Service Request 148 149 ISV 150 Independent Software Vendor 151 152 KMD 153 Kernel Mode Driver 154 155 LB 156 Line Buffer 157 158 LFC 159 Low Framerate Compensation 160 161 LTTPR 162 Link Training Tunable Phy Repeater 163 164 LUT 165 Lookup Table 166 167 MALL 168 Memory Access at Last Level 169 170 MPC/MPCC 171 Multiple pipes and plane combine 172 173 MPO 174 Multi Plane Overlay 175 176 MST 177 Multi Stream Transport 178 179 NBP State 180 Northbridge Power State 181 182 NBIO 183 North Bridge Input/Output 184 185 ODM 186 Output Data Mapping 187 188 OPM 189 Output Protection Manager 190 191 OPP 192 Output Plane Processor 193 194 OPTC 195 Output Pipe Timing Combiner 196 197 OTG 198 Output Timing Generator 199 200 PCON 201 Power Controller 202 203 PGFSM 204 Power Gate Finite State Machine 205 206 PSR 207 Panel Self Refresh 208 209 SCL 210 Scaler 211 212 SDP 213 Scalable Data Port 214 215 SLS 216 Single Large Surface 217 218 SST 219 Single Stream Transport 220 221 TMDS 222 Transition-Minimized Differential Signaling 223 224 TMZ 225 Trusted Memory Zone 226 227 TTU 228 Time to Underflow 229 230 VRR 231 Variable Refresh Rate