tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ5424 TLMM pin controller
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11
12description:
13 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC.
14
15allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19 compatible:
20 const: qcom,ipq5424-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 gpio-reserved-ranges:
29 minItems: 1
30 maxItems: 25
31
32 gpio-line-names:
33 maxItems: 50
34
35patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-ipq5424-tlmm-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-ipq5424-tlmm-state"
42 additionalProperties: false
43
44$defs:
45 qcom-ipq5424-tlmm-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 pattern: "^gpio([0-9]|[1-4][0-9])$"
60 minItems: 1
61 maxItems: 50
62
63 function:
64 description:
65 Specify the alternative function to be configured for the specified
66 pins.
67
68 enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
69 atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
70 audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1,
71 cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest,
72 gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11,
73 mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk,
74 pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake,
75 pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1,
76 prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11,
77 pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0,
78 qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0,
79 qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
80 qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
81 qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
82 sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
83 spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
84
85 required:
86 - pins
87
88required:
89 - compatible
90 - reg
91
92unevaluatedProperties: false
93
94examples:
95 - |
96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97
98 tlmm: pinctrl@1000000 {
99 compatible = "qcom,ipq5424-tlmm";
100 reg = <0x01000000 0x300000>;
101 gpio-controller;
102 #gpio-cells = <0x2>;
103 gpio-ranges = <&tlmm 0 0 50>;
104 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-controller;
106 #interrupt-cells = <0x2>;
107
108 uart1_pins: uart1-state {
109 pins = "gpio43", "gpio44";
110 function = "uart1";
111 drive-strength = <8>;
112 bias-pull-up;
113 };
114 };