tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip PCIe v3 phy
8
9maintainers:
10 - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13 compatible:
14 enum:
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
17
18 reg:
19 maxItems: 1
20
21 clocks:
22 minItems: 1
23 maxItems: 3
24
25 clock-names:
26 minItems: 1
27 maxItems: 3
28
29 data-lanes:
30 description: which lanes (by position) should be mapped to which
31 controller (value). 0 means lane disabled, higher value means used.
32 (controller-number +1 )
33 $ref: /schemas/types.yaml#/definitions/uint32-array
34 minItems: 2
35 maxItems: 16
36 items:
37 minimum: 0
38 maximum: 16
39
40 "#phy-cells":
41 const: 0
42
43 resets:
44 maxItems: 1
45
46 reset-names:
47 const: phy
48
49 phy-supply:
50 description: Single PHY regulator
51
52 rockchip,phy-grf:
53 $ref: /schemas/types.yaml#/definitions/phandle
54 description: phandle to the syscon managing the phy "general register files"
55
56 rockchip,pipe-grf:
57 $ref: /schemas/types.yaml#/definitions/phandle
58 description: phandle to the syscon managing the pipe "general register files"
59
60 rockchip,rx-common-refclk-mode:
61 description: which lanes (by position) should be configured to run in
62 RX common reference clock mode. 0 means disabled, 1 means enabled.
63 $ref: /schemas/types.yaml#/definitions/uint32-array
64 minItems: 1
65 maxItems: 16
66 items:
67 minimum: 0
68 maximum: 1
69
70required:
71 - compatible
72 - reg
73 - rockchip,phy-grf
74 - "#phy-cells"
75
76allOf:
77 - if:
78 properties:
79 compatible:
80 enum:
81 - rockchip,rk3588-pcie3-phy
82 then:
83 properties:
84 clocks:
85 maxItems: 1
86 clock-names:
87 items:
88 - const: pclk
89 else:
90 properties:
91 clocks:
92 minItems: 3
93
94 clock-names:
95 items:
96 - const: refclk_m
97 - const: refclk_n
98 - const: pclk
99
100additionalProperties: false
101
102examples:
103 - |
104 #include <dt-bindings/clock/rk3568-cru.h>
105 pcie30phy: phy@fe8c0000 {
106 compatible = "rockchip,rk3568-pcie3-phy";
107 reg = <0xfe8c0000 0x20000>;
108 #phy-cells = <0>;
109 clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
110 <&pmucru CLK_PCIE30PHY_REF_N>,
111 <&cru PCLK_PCIE30PHY>;
112 clock-names = "refclk_m", "refclk_n", "pclk";
113 resets = <&cru SRST_PCIE30PHY>;
114 reset-names = "phy";
115 rockchip,phy-grf = <&pcie30_phy_grf>;
116 };