tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Keystone 2 IRQ controller IP
8
9maintainers:
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11
12description:
13 On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
14 controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
15 HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx
16 registers. This is one of the component used by the IPC mechanism used on
17 Keystone SOCs.
18
19properties:
20 compatible:
21 const: ti,keystone-irq
22
23 reg:
24 maxItems: 1
25
26 interrupt-controller: true
27
28 '#interrupt-cells':
29 const: 1
30
31 interrupts:
32 maxItems: 1
33
34 ti,syscon-dev:
35 description: Phandle and offset to syscon device
36 $ref: /schemas/types.yaml#/definitions/phandle-array
37 items:
38 - items:
39 - description: Phandle to syscon device control registers
40 - description: Offset to control register
41
42required:
43 - compatible
44 - reg
45 - interrupt-controller
46 - '#interrupt-cells'
47 - interrupts
48 - ti,syscon-dev
49
50additionalProperties: false
51
52examples:
53 - |
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
55
56 interrupt-controller@2a0 {
57 compatible = "ti,keystone-irq";
58 reg = <0x2a0 0x4>;
59 ti,syscon-dev = <&devctrl 0x2a0>;
60 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
61 interrupt-controller;
62 #interrupt-cells = <1>;
63 };