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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3// Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 */
5#ifndef _LINUX_PSE_CONTROLLER_H
6#define _LINUX_PSE_CONTROLLER_H
7
8#include <linux/list.h>
9#include <uapi/linux/ethtool.h>
10
11/* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */
12#define MAX_PI_CURRENT 1920000
13/* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */
14#define MAX_PI_PW 99900
15
16struct phy_device;
17struct pse_controller_dev;
18struct netlink_ext_ack;
19
20/* C33 PSE extended state and substate. */
21struct ethtool_c33_pse_ext_state_info {
22 enum ethtool_c33_pse_ext_state c33_pse_ext_state;
23 union {
24 enum ethtool_c33_pse_ext_substate_error_condition error_condition;
25 enum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;
26 enum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;
27 enum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;
28 enum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;
29 enum ethtool_c33_pse_ext_substate_power_not_available power_not_available;
30 enum ethtool_c33_pse_ext_substate_short_detected short_detected;
31 u32 __c33_pse_ext_substate;
32 };
33};
34
35struct ethtool_c33_pse_pw_limit_range {
36 u32 min;
37 u32 max;
38};
39
40/**
41 * struct pse_control_config - PSE control/channel configuration.
42 *
43 * @podl_admin_control: set PoDL PSE admin control as described in
44 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl
45 * @c33_admin_control: set PSE admin control as described in
46 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl
47 */
48struct pse_control_config {
49 enum ethtool_podl_pse_admin_state podl_admin_control;
50 enum ethtool_c33_pse_admin_state c33_admin_control;
51};
52
53/**
54 * struct pse_admin_state - PSE operational state
55 *
56 * @podl_admin_state: operational state of the PoDL PSE
57 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
58 * @c33_admin_state: operational state of the PSE
59 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
60 */
61struct pse_admin_state {
62 enum ethtool_podl_pse_admin_state podl_admin_state;
63 enum ethtool_c33_pse_admin_state c33_admin_state;
64};
65
66/**
67 * struct pse_pw_status - PSE power detection status
68 *
69 * @podl_pw_status: power detection status of the PoDL PSE.
70 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
71 * @c33_pw_status: power detection status of the PSE.
72 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
73 */
74struct pse_pw_status {
75 enum ethtool_podl_pse_pw_d_status podl_pw_status;
76 enum ethtool_c33_pse_pw_d_status c33_pw_status;
77};
78
79/**
80 * struct pse_ext_state_info - PSE extended state information
81 *
82 * @c33_ext_state_info: extended state information of the PSE
83 */
84struct pse_ext_state_info {
85 struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
86};
87
88/**
89 * struct pse_pw_limit_ranges - PSE power limit configuration range
90 *
91 * @c33_pw_limit_ranges: supported power limit configuration range. The driver
92 * is in charge of the memory allocation.
93 */
94struct pse_pw_limit_ranges {
95 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
96};
97
98/**
99 * struct ethtool_pse_control_status - PSE control/channel status.
100 *
101 * @podl_admin_state: operational state of the PoDL PSE
102 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
103 * @podl_pw_status: power detection status of the PoDL PSE.
104 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
105 * @c33_admin_state: operational state of the PSE
106 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
107 * @c33_pw_status: power detection status of the PSE.
108 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
109 * @c33_pw_class: detected class of a powered PD
110 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification
111 * @c33_actual_pw: power currently delivered by the PSE in mW
112 * IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower
113 * @c33_ext_state_info: extended state information of the PSE
114 * @c33_avail_pw_limit: available power limit of the PSE in mW
115 * IEEE 802.3-2022 145.2.5.4 pse_avail_pwr
116 * @c33_pw_limit_ranges: supported power limit configuration range. The driver
117 * is in charge of the memory allocation
118 * @c33_pw_limit_nb_ranges: number of supported power limit configuration
119 * ranges
120 */
121struct ethtool_pse_control_status {
122 enum ethtool_podl_pse_admin_state podl_admin_state;
123 enum ethtool_podl_pse_pw_d_status podl_pw_status;
124 enum ethtool_c33_pse_admin_state c33_admin_state;
125 enum ethtool_c33_pse_pw_d_status c33_pw_status;
126 u32 c33_pw_class;
127 u32 c33_actual_pw;
128 struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
129 u32 c33_avail_pw_limit;
130 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
131 u32 c33_pw_limit_nb_ranges;
132};
133
134/**
135 * struct pse_controller_ops - PSE controller driver callbacks
136 *
137 * @setup_pi_matrix: setup PI matrix of the PSE controller
138 * @pi_get_admin_state: Get the operational state of the PSE PI. This ops
139 * is mandatory.
140 * @pi_get_pw_status: Get the power detection status of the PSE PI. This
141 * ops is mandatory.
142 * @pi_get_ext_state: Get the extended state of the PSE PI.
143 * @pi_get_pw_class: Get the power class of the PSE PI.
144 * @pi_get_actual_pw: Get actual power of the PSE PI in mW.
145 * @pi_enable: Configure the PSE PI as enabled.
146 * @pi_disable: Configure the PSE PI as disabled.
147 * @pi_get_voltage: Return voltage similarly to get_voltage regulator
148 * callback in uV.
149 * @pi_get_pw_limit: Get the configured power limit of the PSE PI in mW.
150 * @pi_set_pw_limit: Configure the power limit of the PSE PI in mW.
151 * @pi_get_pw_limit_ranges: Get the supported power limit configuration
152 * range. The driver is in charge of the memory
153 * allocation and should return the number of
154 * ranges.
155 */
156struct pse_controller_ops {
157 int (*setup_pi_matrix)(struct pse_controller_dev *pcdev);
158 int (*pi_get_admin_state)(struct pse_controller_dev *pcdev, int id,
159 struct pse_admin_state *admin_state);
160 int (*pi_get_pw_status)(struct pse_controller_dev *pcdev, int id,
161 struct pse_pw_status *pw_status);
162 int (*pi_get_ext_state)(struct pse_controller_dev *pcdev, int id,
163 struct pse_ext_state_info *ext_state_info);
164 int (*pi_get_pw_class)(struct pse_controller_dev *pcdev, int id);
165 int (*pi_get_actual_pw)(struct pse_controller_dev *pcdev, int id);
166 int (*pi_enable)(struct pse_controller_dev *pcdev, int id);
167 int (*pi_disable)(struct pse_controller_dev *pcdev, int id);
168 int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id);
169 int (*pi_get_pw_limit)(struct pse_controller_dev *pcdev,
170 int id);
171 int (*pi_set_pw_limit)(struct pse_controller_dev *pcdev,
172 int id, int max_mW);
173 int (*pi_get_pw_limit_ranges)(struct pse_controller_dev *pcdev, int id,
174 struct pse_pw_limit_ranges *pw_limit_ranges);
175};
176
177struct module;
178struct device_node;
179struct of_phandle_args;
180struct pse_control;
181struct ethtool_pse_control_status;
182
183/* PSE PI pairset pinout can either be Alternative A or Alternative B */
184enum pse_pi_pairset_pinout {
185 ALTERNATIVE_A,
186 ALTERNATIVE_B,
187};
188
189/**
190 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout
191 * alternative ant its phandle
192 *
193 * @pinout: description of the pinout alternative
194 * @np: device node pointer describing the pairset phandle
195 */
196struct pse_pi_pairset {
197 enum pse_pi_pairset_pinout pinout;
198 struct device_node *np;
199};
200
201/**
202 * struct pse_pi - PSE PI (Power Interface) entity as described in
203 * IEEE 802.3-2022 145.2.4
204 *
205 * @pairset: table of the PSE PI pinout alternative for the two pairset
206 * @np: device node pointer of the PSE PI node
207 * @rdev: regulator represented by the PSE PI
208 * @admin_state_enabled: PI enabled state
209 */
210struct pse_pi {
211 struct pse_pi_pairset pairset[2];
212 struct device_node *np;
213 struct regulator_dev *rdev;
214 bool admin_state_enabled;
215};
216
217/**
218 * struct pse_controller_dev - PSE controller entity that might
219 * provide multiple PSE controls
220 * @ops: a pointer to device specific struct pse_controller_ops
221 * @owner: kernel module of the PSE controller driver
222 * @list: internal list of PSE controller devices
223 * @pse_control_head: head of internal list of requested PSE controls
224 * @dev: corresponding driver model device struct
225 * @of_pse_n_cells: number of cells in PSE line specifiers
226 * @nr_lines: number of PSE controls in this controller device
227 * @lock: Mutex for serialization access to the PSE controller
228 * @types: types of the PSE controller
229 * @pi: table of PSE PIs described in this controller device
230 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used
231 */
232struct pse_controller_dev {
233 const struct pse_controller_ops *ops;
234 struct module *owner;
235 struct list_head list;
236 struct list_head pse_control_head;
237 struct device *dev;
238 int of_pse_n_cells;
239 unsigned int nr_lines;
240 struct mutex lock;
241 enum ethtool_pse_types types;
242 struct pse_pi *pi;
243 bool no_of_pse_pi;
244};
245
246#if IS_ENABLED(CONFIG_PSE_CONTROLLER)
247int pse_controller_register(struct pse_controller_dev *pcdev);
248void pse_controller_unregister(struct pse_controller_dev *pcdev);
249struct device;
250int devm_pse_controller_register(struct device *dev,
251 struct pse_controller_dev *pcdev);
252
253struct pse_control *of_pse_control_get(struct device_node *node);
254void pse_control_put(struct pse_control *psec);
255
256int pse_ethtool_get_status(struct pse_control *psec,
257 struct netlink_ext_ack *extack,
258 struct ethtool_pse_control_status *status);
259int pse_ethtool_set_config(struct pse_control *psec,
260 struct netlink_ext_ack *extack,
261 const struct pse_control_config *config);
262int pse_ethtool_set_pw_limit(struct pse_control *psec,
263 struct netlink_ext_ack *extack,
264 const unsigned int pw_limit);
265
266bool pse_has_podl(struct pse_control *psec);
267bool pse_has_c33(struct pse_control *psec);
268
269#else
270
271static inline struct pse_control *of_pse_control_get(struct device_node *node)
272{
273 return ERR_PTR(-ENOENT);
274}
275
276static inline void pse_control_put(struct pse_control *psec)
277{
278}
279
280static inline int pse_ethtool_get_status(struct pse_control *psec,
281 struct netlink_ext_ack *extack,
282 struct ethtool_pse_control_status *status)
283{
284 return -EOPNOTSUPP;
285}
286
287static inline int pse_ethtool_set_config(struct pse_control *psec,
288 struct netlink_ext_ack *extack,
289 const struct pse_control_config *config)
290{
291 return -EOPNOTSUPP;
292}
293
294static inline int pse_ethtool_set_pw_limit(struct pse_control *psec,
295 struct netlink_ext_ack *extack,
296 const unsigned int pw_limit)
297{
298 return -EOPNOTSUPP;
299}
300
301static inline bool pse_has_podl(struct pse_control *psec)
302{
303 return false;
304}
305
306static inline bool pse_has_c33(struct pse_control *psec)
307{
308 return false;
309}
310
311#endif
312
313#endif