Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3
4#ifndef _IONIC_DEV_H_
5#define _IONIC_DEV_H_
6
7#include <linux/atomic.h>
8#include <linux/mutex.h>
9#include <linux/workqueue.h>
10#include <linux/skbuff.h>
11#include <linux/bpf_trace.h>
12
13#include "ionic_if.h"
14#include "ionic_regs.h"
15
16#define IONIC_MAX_TX_DESC 8192
17#define IONIC_MAX_RX_DESC 16384
18#define IONIC_MIN_TXRX_DESC 64
19#define IONIC_DEF_TXRX_DESC 1024
20#define IONIC_RX_FILL_THRESHOLD 16
21#define IONIC_RX_FILL_DIV 8
22#define IONIC_TSO_DESCS_NEEDED 44 /* 64K TSO @1500B */
23#define IONIC_LIFS_MAX 1024
24#define IONIC_WATCHDOG_SECS 5
25#define IONIC_ITR_COAL_USEC_DEFAULT 64
26
27#define IONIC_DEV_CMD_REG_VERSION 1
28#define IONIC_DEV_INFO_REG_COUNT 32
29#define IONIC_DEV_CMD_REG_COUNT 32
30
31#define IONIC_NAPI_DEADLINE (HZ) /* 1 sec */
32#define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */
33#define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
34#define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
35#define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 4) /* 4s */
36
37struct ionic_dev_bar {
38 void __iomem *vaddr;
39 phys_addr_t bus_addr;
40 unsigned long len;
41 int res_index;
42};
43
44#ifndef __CHECKER__
45/* Registers */
46static_assert(sizeof(struct ionic_intr) == 32);
47
48static_assert(sizeof(struct ionic_doorbell) == 8);
49static_assert(sizeof(struct ionic_intr_status) == 8);
50static_assert(sizeof(union ionic_dev_regs) == 4096);
51static_assert(sizeof(union ionic_dev_info_regs) == 2048);
52static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
53static_assert(sizeof(struct ionic_lif_stats) == 1024);
54
55static_assert(sizeof(struct ionic_admin_cmd) == 64);
56static_assert(sizeof(struct ionic_admin_comp) == 16);
57static_assert(sizeof(struct ionic_nop_cmd) == 64);
58static_assert(sizeof(struct ionic_nop_comp) == 16);
59
60/* Device commands */
61static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
62static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
63static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
64static_assert(sizeof(struct ionic_dev_init_comp) == 16);
65static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
66static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
67static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
68static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
69static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
70static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
71static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64);
72
73/* Port commands */
74static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
75static_assert(sizeof(struct ionic_port_identify_comp) == 16);
76static_assert(sizeof(struct ionic_port_init_cmd) == 64);
77static_assert(sizeof(struct ionic_port_init_comp) == 16);
78static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
79static_assert(sizeof(struct ionic_port_reset_comp) == 16);
80static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
81static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
82static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
83static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
84
85/* LIF commands */
86static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
87static_assert(sizeof(struct ionic_lif_init_comp) == 16);
88static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
89static_assert(sizeof(ionic_lif_reset_comp) == 16);
90static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
91static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
92static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
93static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
94
95static_assert(sizeof(struct ionic_q_init_cmd) == 64);
96static_assert(sizeof(struct ionic_q_init_comp) == 16);
97static_assert(sizeof(struct ionic_q_control_cmd) == 64);
98static_assert(sizeof(ionic_q_control_comp) == 16);
99static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
100static_assert(sizeof(struct ionic_q_identify_comp) == 16);
101
102static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
103static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
104static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
105static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
106static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
107static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
108
109/* RDMA commands */
110static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
111static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
112
113/* Events */
114static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
115static_assert(sizeof(union ionic_notifyq_comp) == 64);
116static_assert(sizeof(struct ionic_notifyq_event) == 64);
117static_assert(sizeof(struct ionic_link_change_event) == 64);
118static_assert(sizeof(struct ionic_reset_event) == 64);
119static_assert(sizeof(struct ionic_heartbeat_event) == 64);
120static_assert(sizeof(struct ionic_log_event) == 64);
121
122/* I/O */
123static_assert(sizeof(struct ionic_txq_desc) == 16);
124static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
125static_assert(sizeof(struct ionic_txq_sg_desc_v1) == 256);
126static_assert(sizeof(struct ionic_txq_comp) == 16);
127
128static_assert(sizeof(struct ionic_rxq_desc) == 16);
129static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
130static_assert(sizeof(struct ionic_rxq_comp) == 16);
131static_assert(sizeof(struct ionic_rxq_comp) == sizeof(struct ionic_txq_comp));
132
133/* SR/IOV */
134static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
135static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
136static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
137static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
138static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64);
139static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16);
140#endif /* __CHECKER__ */
141
142struct ionic_devinfo {
143 u8 asic_type;
144 u8 asic_rev;
145 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
146 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
147};
148
149struct ionic_dev {
150 union ionic_dev_info_regs __iomem *dev_info_regs;
151 union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
152 struct ionic_hwstamp_regs __iomem *hwstamp_regs;
153
154 atomic_long_t last_check_time;
155 unsigned long last_hb_time;
156 u32 last_fw_hb;
157 bool fw_hb_ready;
158 bool fw_status_ready;
159 u8 fw_generation;
160 u8 opcode;
161
162 u64 __iomem *db_pages;
163 dma_addr_t phy_db_pages;
164
165 struct ionic_intr __iomem *intr_ctrl;
166 u64 __iomem *intr_status;
167
168 struct mutex cmb_inuse_lock; /* for cmb_inuse */
169 unsigned long *cmb_inuse;
170 dma_addr_t phy_cmb_pages;
171 u32 cmb_npages;
172
173 u32 port_info_sz;
174 struct ionic_port_info *port_info;
175 dma_addr_t port_info_pa;
176
177 struct ionic_devinfo dev_info;
178};
179
180struct ionic_queue;
181struct ionic_qcq;
182
183#define IONIC_MAX_BUF_LEN ((u16)-1)
184#define IONIC_PAGE_SIZE MIN(PAGE_SIZE, IONIC_MAX_BUF_LEN)
185
186#define IONIC_XDP_MAX_LINEAR_MTU (IONIC_PAGE_SIZE - \
187 (VLAN_ETH_HLEN + \
188 XDP_PACKET_HEADROOM + \
189 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
190
191struct ionic_buf_info {
192 struct page *page;
193 dma_addr_t dma_addr;
194 u32 page_offset;
195 u32 len;
196};
197
198#define IONIC_TX_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1)
199#define IONIC_RX_MAX_FRAGS (1 + IONIC_RX_MAX_SG_ELEMS)
200
201struct ionic_tx_desc_info {
202 unsigned int bytes;
203 unsigned int nbufs;
204 struct sk_buff *skb;
205 struct xdp_frame *xdpf;
206 enum xdp_action act;
207 struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1];
208};
209
210struct ionic_rx_desc_info {
211 unsigned int nbufs;
212 struct ionic_buf_info bufs[IONIC_RX_MAX_FRAGS];
213};
214
215struct ionic_admin_desc_info {
216 void *ctx;
217};
218
219#define IONIC_QUEUE_NAME_MAX_SZ 16
220
221struct ionic_queue {
222 struct device *dev;
223 struct ionic_lif *lif;
224 union {
225 void *info;
226 struct ionic_tx_desc_info *tx_info;
227 struct ionic_rx_desc_info *rx_info;
228 struct ionic_admin_desc_info *admin_info;
229 };
230 u64 dbval;
231 unsigned long dbell_deadline;
232 unsigned long dbell_jiffies;
233 u16 head_idx;
234 u16 tail_idx;
235 unsigned int index;
236 unsigned int num_descs;
237 unsigned int max_sg_elems;
238
239 u64 features;
240 unsigned int hw_type;
241 bool xdp_flush;
242 union {
243 void *base;
244 struct ionic_txq_desc *txq;
245 struct ionic_rxq_desc *rxq;
246 struct ionic_admin_cmd *adminq;
247 };
248 union {
249 void *sg_base;
250 struct ionic_txq_sg_desc *txq_sgl;
251 struct ionic_txq_sg_desc_v1 *txq_sgl_v1;
252 struct ionic_rxq_sg_desc *rxq_sgl;
253 };
254 struct xdp_rxq_info *xdp_rxq_info;
255 struct bpf_prog *xdp_prog;
256 struct page_pool *page_pool;
257 struct ionic_queue *partner;
258
259 union {
260 void __iomem *cmb_base;
261 struct ionic_txq_desc __iomem *cmb_txq;
262 struct ionic_rxq_desc __iomem *cmb_rxq;
263 };
264 unsigned int type;
265 unsigned int hw_index;
266 dma_addr_t base_pa;
267 dma_addr_t cmb_base_pa;
268 dma_addr_t sg_base_pa;
269 u64 drop;
270 unsigned int desc_size;
271 unsigned int sg_desc_size;
272 unsigned int pid;
273 char name[IONIC_QUEUE_NAME_MAX_SZ];
274} ____cacheline_aligned_in_smp;
275
276#define IONIC_INTR_INDEX_NOT_ASSIGNED -1
277#define IONIC_INTR_NAME_MAX_SZ 32
278
279struct ionic_intr_info {
280 char name[IONIC_INTR_NAME_MAX_SZ];
281 u64 rearm_count;
282 unsigned int index;
283 unsigned int vector;
284 u32 dim_coal_hw;
285 cpumask_var_t *affinity_mask;
286 struct irq_affinity_notify aff_notify;
287};
288
289struct ionic_cq {
290 struct ionic_lif *lif;
291 struct ionic_queue *bound_q;
292 struct ionic_intr_info *bound_intr;
293 u16 tail_idx;
294 bool done_color;
295 unsigned int num_descs;
296 unsigned int desc_size;
297 void *base;
298 dma_addr_t base_pa;
299 struct ionic_dev *idev;
300} ____cacheline_aligned_in_smp;
301
302struct ionic;
303
304static inline void ionic_intr_init(struct ionic_dev *idev,
305 struct ionic_intr_info *intr,
306 unsigned long index)
307{
308 ionic_intr_clean(idev->intr_ctrl, index);
309 intr->index = index;
310}
311
312static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
313{
314 unsigned int avail = q->tail_idx;
315
316 if (q->head_idx >= avail)
317 avail += q->num_descs - q->head_idx - 1;
318 else
319 avail -= q->head_idx + 1;
320
321 return avail;
322}
323
324static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
325{
326 return ionic_q_space_avail(q) >= want;
327}
328
329void ionic_init_devinfo(struct ionic *ionic);
330int ionic_dev_setup(struct ionic *ionic);
331void ionic_dev_teardown(struct ionic *ionic);
332
333void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
334u8 ionic_dev_cmd_status(struct ionic_dev *idev);
335bool ionic_dev_cmd_done(struct ionic_dev *idev);
336void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
337
338void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
339void ionic_dev_cmd_init(struct ionic_dev *idev);
340void ionic_dev_cmd_reset(struct ionic_dev *idev);
341
342void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
343void ionic_dev_cmd_port_init(struct ionic_dev *idev);
344void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
345void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
346void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
347void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
348void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
349void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
350
351int ionic_set_vf_config(struct ionic *ionic, int vf,
352 struct ionic_vf_setattr_cmd *vfc);
353
354void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
355 u16 lif_type, u8 qtype, u8 qver);
356void ionic_vf_start(struct ionic *ionic);
357void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
358void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
359 dma_addr_t addr);
360void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
361void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
362 u16 lif_index, u16 intr_index);
363
364int ionic_db_page_num(struct ionic_lif *lif, int pid);
365
366int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order);
367void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);
368
369int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
370 struct ionic_intr_info *intr,
371 unsigned int num_descs, size_t desc_size);
372void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa);
373void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);
374typedef bool (*ionic_cq_cb)(struct ionic_cq *cq);
375typedef void (*ionic_cq_done_cb)(void *done_arg);
376unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
377 ionic_cq_cb cb, ionic_cq_done_cb done_cb,
378 void *done_arg);
379unsigned int ionic_tx_cq_service(struct ionic_cq *cq,
380 unsigned int work_to_do,
381 bool in_napi);
382
383int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
384 struct ionic_queue *q, unsigned int index, const char *name,
385 unsigned int num_descs, size_t desc_size,
386 size_t sg_desc_size, unsigned int pid);
387void ionic_q_post(struct ionic_queue *q, bool ring_doorbell);
388bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos);
389
390int ionic_heartbeat_check(struct ionic *ionic);
391bool ionic_is_fw_running(struct ionic_dev *idev);
392void ionic_doorbell_napi_work(struct work_struct *work);
393void ionic_queue_doorbell_check(struct ionic *ionic, int delay);
394
395bool ionic_adminq_poke_doorbell(struct ionic_queue *q);
396bool ionic_txq_poke_doorbell(struct ionic_queue *q);
397bool ionic_rxq_poke_doorbell(struct ionic_queue *q);
398
399#endif /* _IONIC_DEV_H_ */