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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef __IRIS_PLATFORM_COMMON_H__
7#define __IRIS_PLATFORM_COMMON_H__
8
9#include <linux/bits.h>
10
11struct iris_core;
12struct iris_inst;
13
14#define IRIS_PAS_ID 9
15#define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */
16#define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */
17
18#define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma))
19#define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8)
20#define CODED_FRAMES_PROGRESSIVE 0x0
21#define DEFAULT_MAX_HOST_BUF_COUNT 64
22#define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256
23#define DEFAULT_FPS 30
24
25enum stage_type {
26 STAGE_1 = 1,
27 STAGE_2 = 2,
28};
29
30enum pipe_type {
31 PIPE_1 = 1,
32 PIPE_2 = 2,
33 PIPE_4 = 4,
34};
35
36extern struct iris_platform_data sm8250_data;
37extern struct iris_platform_data sm8550_data;
38
39enum platform_clk_type {
40 IRIS_AXI_CLK,
41 IRIS_CTRL_CLK,
42 IRIS_HW_CLK,
43};
44
45struct platform_clk_data {
46 enum platform_clk_type clk_type;
47 const char *clk_name;
48};
49
50struct tz_cp_config {
51 u32 cp_start;
52 u32 cp_size;
53 u32 cp_nonpixel_start;
54 u32 cp_nonpixel_size;
55};
56
57struct ubwc_config_data {
58 u32 max_channels;
59 u32 mal_length;
60 u32 highest_bank_bit;
61 u32 bank_swzl_level;
62 u32 bank_swz2_level;
63 u32 bank_swz3_level;
64 u32 bank_spreading;
65};
66
67struct platform_inst_caps {
68 u32 min_frame_width;
69 u32 max_frame_width;
70 u32 min_frame_height;
71 u32 max_frame_height;
72 u32 max_mbpf;
73 u32 mb_cycles_vsp;
74 u32 mb_cycles_vpp;
75 u32 mb_cycles_fw;
76 u32 mb_cycles_fw_vpp;
77 u32 num_comv;
78};
79
80enum platform_inst_fw_cap_type {
81 PROFILE = 1,
82 LEVEL,
83 INPUT_BUF_HOST_MAX_COUNT,
84 STAGE,
85 PIPE,
86 POC,
87 CODED_FRAMES,
88 BIT_DEPTH,
89 RAP_FRAME,
90 DEBLOCK,
91 INST_FW_CAP_MAX,
92};
93
94enum platform_inst_fw_cap_flags {
95 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0),
96 CAP_FLAG_MENU = BIT(1),
97 CAP_FLAG_INPUT_PORT = BIT(2),
98 CAP_FLAG_OUTPUT_PORT = BIT(3),
99 CAP_FLAG_CLIENT_SET = BIT(4),
100 CAP_FLAG_BITMASK = BIT(5),
101 CAP_FLAG_VOLATILE = BIT(6),
102};
103
104struct platform_inst_fw_cap {
105 enum platform_inst_fw_cap_type cap_id;
106 s64 min;
107 s64 max;
108 s64 step_or_mask;
109 s64 value;
110 u32 hfi_id;
111 enum platform_inst_fw_cap_flags flags;
112 int (*set)(struct iris_inst *inst,
113 enum platform_inst_fw_cap_type cap_id);
114};
115
116struct bw_info {
117 u32 mbs_per_sec;
118 u32 bw_ddr;
119};
120
121struct iris_core_power {
122 u64 clk_freq;
123 u64 icc_bw;
124};
125
126struct iris_inst_power {
127 u64 min_freq;
128 u32 icc_bw;
129};
130
131struct icc_vote_data {
132 u32 height, width;
133 u32 fps;
134};
135
136enum platform_pm_domain_type {
137 IRIS_CTRL_POWER_DOMAIN,
138 IRIS_HW_POWER_DOMAIN,
139};
140
141struct iris_platform_data {
142 void (*init_hfi_command_ops)(struct iris_core *core);
143 void (*init_hfi_response_ops)(struct iris_core *core);
144 struct iris_inst *(*get_instance)(void);
145 const struct vpu_ops *vpu_ops;
146 void (*set_preset_registers)(struct iris_core *core);
147 const struct icc_info *icc_tbl;
148 unsigned int icc_tbl_size;
149 const struct bw_info *bw_tbl_dec;
150 unsigned int bw_tbl_dec_size;
151 const char * const *pmdomain_tbl;
152 unsigned int pmdomain_tbl_size;
153 const char * const *opp_pd_tbl;
154 unsigned int opp_pd_tbl_size;
155 const struct platform_clk_data *clk_tbl;
156 unsigned int clk_tbl_size;
157 const char * const *clk_rst_tbl;
158 unsigned int clk_rst_tbl_size;
159 u64 dma_mask;
160 const char *fwname;
161 u32 pas_id;
162 struct platform_inst_caps *inst_caps;
163 struct platform_inst_fw_cap *inst_fw_caps;
164 u32 inst_fw_caps_size;
165 struct tz_cp_config *tz_cp_config_data;
166 u32 core_arch;
167 u32 hw_response_timeout;
168 struct ubwc_config_data *ubwc_config;
169 u32 num_vpp_pipe;
170 u32 max_session_count;
171 u32 max_core_mbpf;
172 const u32 *input_config_params;
173 unsigned int input_config_params_size;
174 const u32 *output_config_params;
175 unsigned int output_config_params_size;
176 const u32 *dec_input_prop;
177 unsigned int dec_input_prop_size;
178 const u32 *dec_output_prop;
179 unsigned int dec_output_prop_size;
180 const u32 *dec_ip_int_buf_tbl;
181 unsigned int dec_ip_int_buf_tbl_size;
182 const u32 *dec_op_int_buf_tbl;
183 unsigned int dec_op_int_buf_tbl_size;
184};
185
186#endif