tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8
9#include <drm/drm_device.h>
10#include <drm/drm_drv.h>
11#include <drm/drm_managed.h>
12#include <drm/drm_mm.h>
13#include <drm/drm_print.h>
14
15#include <linux/pci.h>
16#include <linux/xarray.h>
17#include <uapi/drm/ivpu_accel.h>
18
19#include "ivpu_mmu_context.h"
20#include "ivpu_ipc.h"
21
22#define DRIVER_NAME "intel_vpu"
23#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24
25#define PCI_DEVICE_ID_MTL 0x7d1d
26#define PCI_DEVICE_ID_ARL 0xad1d
27#define PCI_DEVICE_ID_LNL 0x643e
28#define PCI_DEVICE_ID_PTL_P 0xb03e
29
30#define IVPU_HW_IP_37XX 37
31#define IVPU_HW_IP_40XX 40
32#define IVPU_HW_IP_50XX 50
33#define IVPU_HW_IP_60XX 60
34
35#define IVPU_HW_IP_REV_LNL_B0 4
36
37#define IVPU_HW_BTRS_MTL 1
38#define IVPU_HW_BTRS_LNL 2
39
40#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
41/* SSID 1 is used by the VPU to represent reserved context */
42#define IVPU_RESERVED_CONTEXT_MMU_SSID 1
43#define IVPU_USER_CONTEXT_MIN_SSID 2
44#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
45
46#define IVPU_MIN_DB 1
47#define IVPU_MAX_DB 255
48
49#define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
50#define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
51
52#define IVPU_NUM_PRIORITIES 4
53#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
54
55#define IVPU_CMDQ_MIN_ID 1
56#define IVPU_CMDQ_MAX_ID 255
57
58#define IVPU_PLATFORM_SILICON 0
59#define IVPU_PLATFORM_SIMICS 2
60#define IVPU_PLATFORM_FPGA 3
61#define IVPU_PLATFORM_HSLE 4
62#define IVPU_PLATFORM_INVALID 8
63
64#define IVPU_SCHED_MODE_AUTO -1
65
66#define IVPU_DBG_REG BIT(0)
67#define IVPU_DBG_IRQ BIT(1)
68#define IVPU_DBG_MMU BIT(2)
69#define IVPU_DBG_FILE BIT(3)
70#define IVPU_DBG_MISC BIT(4)
71#define IVPU_DBG_FW_BOOT BIT(5)
72#define IVPU_DBG_PM BIT(6)
73#define IVPU_DBG_IPC BIT(7)
74#define IVPU_DBG_BO BIT(8)
75#define IVPU_DBG_JOB BIT(9)
76#define IVPU_DBG_JSM BIT(10)
77#define IVPU_DBG_KREF BIT(11)
78#define IVPU_DBG_RPM BIT(12)
79#define IVPU_DBG_MMU_MAP BIT(13)
80
81#define ivpu_err(vdev, fmt, ...) \
82 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
83
84#define ivpu_err_ratelimited(vdev, fmt, ...) \
85 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
86
87#define ivpu_warn(vdev, fmt, ...) \
88 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
89
90#define ivpu_warn_ratelimited(vdev, fmt, ...) \
91 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
92
93#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
94
95#define ivpu_dbg(vdev, type, fmt, args...) do { \
96 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
97 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
98} while (0)
99
100#define IVPU_WA(wa_name) (vdev->wa.wa_name)
101
102#define IVPU_PRINT_WA(wa_name) do { \
103 if (IVPU_WA(wa_name)) \
104 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
105} while (0)
106
107struct ivpu_wa_table {
108 bool punit_disabled;
109 bool clear_runtime_mem;
110 bool interrupt_clear_with_0;
111 bool disable_clock_relinquish;
112 bool disable_d0i3_msg;
113 bool wp0_during_power_up;
114 bool disable_d0i2;
115};
116
117struct ivpu_hw_info;
118struct ivpu_mmu_info;
119struct ivpu_fw_info;
120struct ivpu_ipc_info;
121struct ivpu_pm_info;
122
123struct ivpu_device {
124 struct drm_device drm;
125 void __iomem *regb;
126 void __iomem *regv;
127 u32 platform;
128 u32 irq;
129
130 struct ivpu_wa_table wa;
131 struct ivpu_hw_info *hw;
132 struct ivpu_mmu_info *mmu;
133 struct ivpu_fw_info *fw;
134 struct ivpu_ipc_info *ipc;
135 struct ivpu_pm_info *pm;
136
137 struct ivpu_mmu_context gctx;
138 struct ivpu_mmu_context rctx;
139 struct mutex context_list_lock; /* Protects user context addition/removal */
140 struct xarray context_xa;
141 struct xa_limit context_xa_limit;
142
143 struct xarray db_xa;
144 struct xa_limit db_limit;
145 u32 db_next;
146
147 struct work_struct irq_ipc_work;
148 struct work_struct irq_dct_work;
149 struct work_struct context_abort_work;
150
151 struct mutex bo_list_lock; /* Protects bo_list */
152 struct list_head bo_list;
153
154 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
155 struct xarray submitted_jobs_xa;
156 struct ivpu_ipc_consumer job_done_consumer;
157
158 atomic64_t unique_id_counter;
159
160 ktime_t busy_start_ts;
161 ktime_t busy_time;
162
163 struct {
164 int boot;
165 int jsm;
166 int tdr;
167 int autosuspend;
168 int d0i3_entry_msg;
169 int state_dump_msg;
170 } timeout;
171};
172
173/*
174 * file_priv has its own refcount (ref) that allows user space to close the fd
175 * without blocking even if VPU is still processing some jobs.
176 */
177struct ivpu_file_priv {
178 struct kref ref;
179 struct ivpu_device *vdev;
180 struct mutex lock; /* Protects cmdq */
181 struct xarray cmdq_xa;
182 struct ivpu_mmu_context ctx;
183 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
184 struct list_head ms_instance_list;
185 struct ivpu_bo *ms_info_bo;
186 struct xa_limit job_limit;
187 u32 job_id_next;
188 struct xa_limit cmdq_limit;
189 u32 cmdq_id_next;
190 bool has_mmu_faults;
191 bool bound;
192 bool aborted;
193};
194
195extern int ivpu_dbg_mask;
196extern u8 ivpu_pll_min_ratio;
197extern u8 ivpu_pll_max_ratio;
198extern int ivpu_sched_mode;
199extern bool ivpu_disable_mmu_cont_pages;
200extern bool ivpu_force_snoop;
201
202#define IVPU_TEST_MODE_FW_TEST BIT(0)
203#define IVPU_TEST_MODE_NULL_HW BIT(1)
204#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
205#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
206#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
207#define IVPU_TEST_MODE_MIP_DISABLE BIT(6)
208#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
209#define IVPU_TEST_MODE_TURBO BIT(9)
210#define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(10)
211#define IVPU_TEST_MODE_CLK_RELINQ_ENABLE BIT(11)
212#define IVPU_TEST_MODE_D0I2_DISABLE BIT(12)
213extern int ivpu_test_mode;
214
215struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
216void ivpu_file_priv_put(struct ivpu_file_priv **link);
217
218int ivpu_boot(struct ivpu_device *vdev);
219int ivpu_shutdown(struct ivpu_device *vdev);
220void ivpu_prepare_for_reset(struct ivpu_device *vdev);
221bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
222
223static inline u8 ivpu_revision(struct ivpu_device *vdev)
224{
225 return to_pci_dev(vdev->drm.dev)->revision;
226}
227
228static inline u16 ivpu_device_id(struct ivpu_device *vdev)
229{
230 return to_pci_dev(vdev->drm.dev)->device;
231}
232
233static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
234{
235 switch (ivpu_device_id(vdev)) {
236 case PCI_DEVICE_ID_MTL:
237 case PCI_DEVICE_ID_ARL:
238 return IVPU_HW_IP_37XX;
239 case PCI_DEVICE_ID_LNL:
240 return IVPU_HW_IP_40XX;
241 case PCI_DEVICE_ID_PTL_P:
242 return IVPU_HW_IP_50XX;
243 default:
244 dump_stack();
245 ivpu_err(vdev, "Unknown NPU IP generation\n");
246 return 0;
247 }
248}
249
250static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
251{
252 switch (ivpu_device_id(vdev)) {
253 case PCI_DEVICE_ID_MTL:
254 case PCI_DEVICE_ID_ARL:
255 return IVPU_HW_BTRS_MTL;
256 case PCI_DEVICE_ID_LNL:
257 case PCI_DEVICE_ID_PTL_P:
258 return IVPU_HW_BTRS_LNL;
259 default:
260 dump_stack();
261 ivpu_err(vdev, "Unknown buttress generation\n");
262 return 0;
263 }
264}
265
266static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
267{
268 return container_of(dev, struct ivpu_device, drm);
269}
270
271static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
272{
273 struct xa_limit ctx_limit = vdev->context_xa_limit;
274
275 return (ctx_limit.max - ctx_limit.min + 1);
276}
277
278static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
279{
280 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
281 return vdev->platform;
282}
283
284static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
285{
286 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
287}
288
289static inline bool ivpu_is_simics(struct ivpu_device *vdev)
290{
291 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
292}
293
294static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
295{
296 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
297 ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
298}
299
300static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
301{
302 return ivpu_force_snoop;
303}
304
305#endif /* __IVPU_DRV_H__ */