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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Contains register definitions common to the Book E PowerPC
4 * specification.
5 *
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_POWERPC_REG_BOOKE_H__
10#define __ASM_POWERPC_REG_BOOKE_H__
11
12#include <asm/ppc-opcode.h>
13
14/* Machine State Register (MSR) Fields */
15#define MSR_GS_LG 28 /* Guest state */
16#define MSR_UCLE_LG 26 /* User-mode cache lock enable */
17#define MSR_SPE_LG 25 /* Enable SPE */
18#define MSR_DWE_LG 10 /* Debug Wait Enable */
19#define MSR_UBLE_LG 10 /* BTB lock enable (e500) */
20#define MSR_IS_LG MSR_IR_LG /* Instruction Space */
21#define MSR_DS_LG MSR_DR_LG /* Data Space */
22#define MSR_PMM_LG 2 /* Performance monitor mark bit */
23#define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
24
25#define MSR_GS __MASK(MSR_GS_LG)
26#define MSR_UCLE __MASK(MSR_UCLE_LG)
27#define MSR_SPE __MASK(MSR_SPE_LG)
28#define MSR_DWE __MASK(MSR_DWE_LG)
29#define MSR_UBLE __MASK(MSR_UBLE_LG)
30#define MSR_IS __MASK(MSR_IS_LG)
31#define MSR_DS __MASK(MSR_DS_LG)
32#define MSR_PMM __MASK(MSR_PMM_LG)
33#define MSR_CM __MASK(MSR_CM_LG)
34
35#if defined(CONFIG_PPC_BOOK3E_64)
36#define MSR_64BIT MSR_CM
37
38#define MSR_ (MSR_ME | MSR_RI | MSR_CE)
39#define MSR_KERNEL (MSR_ | MSR_64BIT)
40#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
41#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
42#else
43#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
44#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
45#endif
46
47/* Special Purpose Registers (SPRNs)*/
48#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51#define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
57#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
58#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
59#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
60#define SPRN_EPCR 0x133 /* Embedded Processor Control Register */
61#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
62#define SPRN_DBCR4 0x233 /* Debug Control Register 4 */
63#define SPRN_MSRP 0x137 /* MSR Protect Register */
64#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
65#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
66#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
67#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
68#define SPRN_LPID 0x152 /* Logical Partition ID */
69#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
70#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
71#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
72#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
73#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
74#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */
75#define SPRN_GSPRG0 0x170 /* Guest SPRG0 */
76#define SPRN_GSPRG1 0x171 /* Guest SPRG1 */
77#define SPRN_GSPRG2 0x172 /* Guest SPRG2 */
78#define SPRN_GSPRG3 0x173 /* Guest SPRG3 */
79#define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
80#define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
81#define SPRN_GSRR0 0x17A /* Guest SRR0 */
82#define SPRN_GSRR1 0x17B /* Guest SRR1 */
83#define SPRN_GEPR 0x17C /* Guest EPR */
84#define SPRN_GDEAR 0x17D /* Guest DEAR */
85#define SPRN_GPIR 0x17E /* Guest PIR */
86#define SPRN_GESR 0x17F /* Guest Exception Syndrome Register */
87#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
88#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
89#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
90#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
91#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
92#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
93#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
94#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
95#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
96#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
97#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
98#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
99#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
100#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
101#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
102#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
103#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
104#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
105#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
106#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
107#define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
108#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */
109#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */
110#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */
111#define SPRN_GIVOR8 0x1BB /* Guest IVOR8 */
112#define SPRN_GIVOR13 0x1BC /* Guest IVOR13 */
113#define SPRN_GIVOR14 0x1BD /* Guest IVOR14 */
114#define SPRN_GIVPR 0x1BF /* Guest IVPR */
115#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
116#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
117#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
118#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
119#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
120#define SPRN_ATB 0x20E /* Alternate Time Base */
121#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
122#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
123#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
124#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
125#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
126#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
127#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
128#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
129#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
130#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132#define SPRN_MCSR 0x23C /* Machine Check Status Register */
133#define SPRN_MCAR 0x23D /* Machine Check Address Register */
134#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
135#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
136#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
137#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
138#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
139#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
140#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
141#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
142#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
143#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
144#define SPRN_MAS5 0x153 /* MMU Assist Register 5 */
145#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
146#define SPRN_PID1 0x279 /* Process ID Register 1 */
147#define SPRN_PID2 0x27A /* Process ID Register 2 */
148#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
149#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
150#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */
151#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */
152#define SPRN_EPR 0x2BE /* External Proxy Register */
153#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
154#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
155#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
156#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
157#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
158#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
159#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
160#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161#define SPRN_SLER 0x3BB /* Little-endian real mode */
162#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
163#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
164#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
165#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
166#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
167#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
168#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
169#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
170#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
171#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
172#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
173#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
174#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
175#define SPRN_SVR 0x3FF /* System Version Register */
176
177/*
178 * SPRs which have conflicting definitions on true Book E versus classic.
179 */
180#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
181#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
182#define SPRN_DEAR 0x03D /* Data Error Address Register */
183#define SPRN_ESR 0x03E /* Exception Syndrome Register */
184#define SPRN_PIR 0x11E /* Processor Identification Register */
185#define SPRN_DBSR 0x130 /* Debug Status Register */
186#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
187#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
188#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
189#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
190#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
191#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
192#define SPRN_TSR 0x150 /* Timer Status Register */
193#define SPRN_TCR 0x154 /* Timer Control Register */
194#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
195
196/* Bit definitions for CCR1. */
197#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
198#define CCR1_TCS 0x00000080 /* Timer Clock Select */
199
200/* Bit definitions for PWRMGTCR0. */
201#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
202#define PWRMGTCR0_PW20_ENT_SHIFT 8
203#define PWRMGTCR0_PW20_ENT 0x3F00
204#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
205#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
206#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
207
208/* Bit definitions for the MCSR. */
209#define MCSR_MCS 0x80000000 /* Machine Check Summary */
210#define MCSR_IB 0x40000000 /* Instruction PLB Error */
211#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
212#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
213#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
214#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
216#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
217#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
218
219#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */
220#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
221#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
222
223#ifdef CONFIG_PPC_E500
224/* All e500 */
225#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
226#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
227
228/* e500v1/v2 */
229#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
230#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
231#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
232#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
233#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
234#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
235#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
236#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
237#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
238#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
239
240/* e500mc */
241#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
242#define MCSR_L2MMU_MHIT 0x08000000UL /* Hit on multiple TLB entries */
243#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
244#define MCSR_MAV 0x00080000UL /* MCAR address valid */
245#define MCSR_MEA 0x00040000UL /* MCAR is effective address */
246#define MCSR_IF 0x00010000UL /* Instruction Fetch */
247#define MCSR_LD 0x00008000UL /* Load */
248#define MCSR_ST 0x00004000UL /* Store */
249#define MCSR_LDG 0x00002000UL /* Guarded Load */
250#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
251#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
252
253#define MSRP_UCLEP 0x04000000 /* Protect MSR[UCLE] */
254#define MSRP_DEP 0x00000200 /* Protect MSR[DE] */
255#define MSRP_PMMP 0x00000004 /* Protect MSR[PMM] */
256#endif
257
258/* Bit definitions for the HID1 */
259#ifdef CONFIG_PPC_E500
260/* e500v1/v2 */
261#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */
262#define HID1_RFXE 0x00020000 /* Read fault exception enable */
263#define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */
264#define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */
265#define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */
266#define HID1_ABE 0x00001000 /* Address broadcast enable */
267#define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
268#define HID1_ATS 0x00000080 /* Atomic status */
269#define HID1_MID_MASK 0x0000000f /* MID input pins */
270#endif
271
272/* Bit definitions for the DBSR. */
273#define DBSR_IDE 0x80000000 /* Imprecise Debug Event */
274#define DBSR_MRR 0x30000000 /* Most Recent Reset */
275#define DBSR_IC 0x08000000 /* Instruction Completion */
276#define DBSR_BT 0x04000000 /* Branch Taken */
277#define DBSR_IRPT 0x02000000 /* Exception Debug Event */
278#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
279#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
280#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
281#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
282#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
283#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
284#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
285#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
286#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
287#define DBSR_RET 0x00008000 /* Return Debug Event */
288#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
289#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
290#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
291#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
292
293/* Bit definitions related to the ESR. */
294#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
295#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
296#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
297#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
298#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
299#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
300#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
301#define ESR_PTR 0x02000000 /* Program Exception - Trap */
302#define ESR_FP 0x01000000 /* Floating Point Operation */
303#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
304#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
305#define ESR_ST 0x00800000 /* Store Operation */
306#define ESR_DLK 0x00200000 /* Data Cache Locking */
307#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
308#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
309#define ESR_BO 0x00020000 /* Byte Ordering */
310#define ESR_SPV 0x00000080 /* Signal Processing operation */
311
312/* Bit definitions related to the DBCR0. */
313#define DBCR0_EDM 0x80000000 /* External Debug Mode */
314#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
315#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
316/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
317#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
318#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
319#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
320#define DBCR0_RST_NONE 0x00000000 /* No Reset */
321#define DBCR0_ICMP 0x08000000 /* Instruction Completion */
322#define DBCR0_IC DBCR0_ICMP
323#define DBCR0_BRT 0x04000000 /* Branch Taken */
324#define DBCR0_BT DBCR0_BRT
325#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */
326#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
327#define DBCR0_TIE DBCR0_TDE
328#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
329#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
330#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
331#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
332#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */
333#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */
334#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */
335#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */
336#define DBCR0_RET 0x00008000 /* Return Debug Event */
337#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
338#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
339#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
340
341#define dbcr_dac(task) ((task)->thread.debug.dbcr0)
342#define DBCR_DAC1R DBCR0_DAC1R
343#define DBCR_DAC1W DBCR0_DAC1W
344#define DBCR_DAC2R DBCR0_DAC2R
345#define DBCR_DAC2W DBCR0_DAC2W
346
347/* Bit definitions related to the DBCR1. */
348#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */
349#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */
350#define DBCR1_IAC1ER_01 0x10000000 /* reserved */
351#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
352#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
353#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */
354#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */
355#define DBCR1_IAC2ER_01 0x01000000 /* reserved */
356#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
357#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
358#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
359#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
360#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
361#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */
362#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */
363#define DBCR1_IAC3ER_01 0x00001000 /* reserved */
364#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
365#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
366#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */
367#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */
368#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
369#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
370#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
371#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
372#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
373#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
374
375#define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
376#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
377#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
378#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
379#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */
380#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */
381#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
382
383/* Bit definitions related to the DBCR2. */
384#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */
385#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */
386#define DBCR2_DAC2US 0x0C000000 /* Data Addr Cmp 2 Sup/User */
387#define DBCR2_DAC2ER 0x03000000 /* Data Addr Cmp 2 Eff/Real */
388#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
389#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
390#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
391#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
392#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
393#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
394#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */
395#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
396#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */
397#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */
398#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */
399#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */
400#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */
401
402/*
403 * Are there any active Debug Events represented in the
404 * Debug Control Registers?
405 */
406#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
407 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
408 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)
409#define DBCR1_ACTIVE_EVENTS 0
410
411#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
412 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
413
414/* Bit definitions related to the TCR. */
415#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
416#define TCR_WP_MASK TCR_WP(3)
417#define WP_2_17 0 /* 2^17 clocks */
418#define WP_2_21 1 /* 2^21 clocks */
419#define WP_2_25 2 /* 2^25 clocks */
420#define WP_2_29 3 /* 2^29 clocks */
421#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
422#define TCR_WRC_MASK TCR_WRC(3)
423#define WRC_NONE 0 /* No reset will occur */
424#define WRC_CORE 1 /* Core reset will occur */
425#define WRC_CHIP 2 /* Chip reset will occur */
426#define WRC_SYSTEM 3 /* System reset will occur */
427#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
428#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
429#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
430#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
431#define TCR_FP_MASK TCR_FP(3)
432#define FP_2_9 0 /* 2^9 clocks */
433#define FP_2_13 1 /* 2^13 clocks */
434#define FP_2_17 2 /* 2^17 clocks */
435#define FP_2_21 3 /* 2^21 clocks */
436#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
437#define TCR_ARE 0x00400000 /* Auto Reload Enable */
438
439#ifdef CONFIG_PPC_E500
440#define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \
441 (((tcr) & 0x1E0000) >> 15))
442#else
443#define TCR_GET_WP(tcr) (((tcr) & 0xC0000000) >> 30)
444#endif
445
446/* Bit definitions for the TSR. */
447#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
448#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
449#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
450#define WRS_NONE 0 /* No WDT reset occurred */
451#define WRS_CORE 1 /* WDT forced core reset */
452#define WRS_CHIP 2 /* WDT forced chip reset */
453#define WRS_SYSTEM 3 /* WDT forced system reset */
454#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
455#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
456#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
457
458/* Bit definitions for the DCCR. */
459#define DCCR_NOCACHE 0 /* Noncacheable */
460#define DCCR_CACHE 1 /* Cacheable */
461
462/* Bit definitions for DCWR. */
463#define DCWR_COPY 0 /* Copy-back */
464#define DCWR_WRITE 1 /* Write-through */
465
466/* Bit definitions for ICCR. */
467#define ICCR_NOCACHE 0 /* Noncacheable */
468#define ICCR_CACHE 1 /* Cacheable */
469
470/* Bit definitions for L1CSR0. */
471#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
472#define L1CSR0_CUL 0x00000400 /* Data Cache Unable to Lock */
473#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
474#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
475#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
476#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
477
478/* Bit definitions for L1CSR1. */
479#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
480#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
481#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
482#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
483
484/* Bit definitions for L1CSR2. */
485#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
486
487/* Bit definitions for BUCSR. */
488#define BUCSR_STAC_EN 0x01000000 /* Segment Target Address Cache */
489#define BUCSR_LS_EN 0x00400000 /* Link Stack */
490#define BUCSR_BBFI 0x00000200 /* Branch Buffer flash invalidate */
491#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
492#define BUCSR_INIT (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
493
494/* Bit definitions for L2CSR0. */
495#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
496#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
497#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
498#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
499#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
500#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
501#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
502#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
503#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
504#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
505#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
506#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
507
508/* Bit definitions for SGR. */
509#define SGR_NORMAL 0 /* Speculative fetching allowed. */
510#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
511
512/* Bit definitions for EPCR */
513#define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt
514 * directed to Guest state */
515#define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt
516 * directed to guest state */
517#define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt
518 * directed to guest state */
519#define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt
520 * directed to guest state */
521#define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt
522 * directed to guest state */
523#define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */
524#define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode
525 * (copied to MSR:CM on intr) */
526#define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */
527#define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management
528 * instructions */
529#define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates
530 * for hypervisor */
531
532/* Bit definitions for EPLC/EPSC */
533#define EPC_EPR 0x80000000 /* 1 = user, 0 = kernel */
534#define EPC_EPR_SHIFT 31
535#define EPC_EAS 0x40000000 /* Address Space */
536#define EPC_EAS_SHIFT 30
537#define EPC_EGS 0x20000000 /* 1 = guest, 0 = hypervisor */
538#define EPC_EGS_SHIFT 29
539#define EPC_ELPID 0x00ff0000
540#define EPC_ELPID_SHIFT 16
541#define EPC_EPID 0x00003fff
542#define EPC_EPID_SHIFT 0
543
544/* Some 476 specific registers */
545#define SPRN_SSPCR 830
546#define SPRN_USPCR 831
547#define SPRN_ISPCR 829
548#define SPRN_MMUBE0 820
549#define MMUBE0_IBE0_SHIFT 24
550#define MMUBE0_IBE1_SHIFT 16
551#define MMUBE0_IBE2_SHIFT 8
552#define MMUBE0_VBE0 0x00000004
553#define MMUBE0_VBE1 0x00000002
554#define MMUBE0_VBE2 0x00000001
555#define SPRN_MMUBE1 821
556#define MMUBE1_IBE3_SHIFT 24
557#define MMUBE1_IBE4_SHIFT 16
558#define MMUBE1_IBE5_SHIFT 8
559#define MMUBE1_VBE3 0x00000004
560#define MMUBE1_VBE4 0x00000002
561#define MMUBE1_VBE5 0x00000001
562
563#define TMRN_TMCFG0 16 /* Thread Management Configuration Register 0 */
564#define TMRN_TMCFG0_NPRIBITS 0x003f0000 /* Bits of thread priority */
565#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
566#define TMRN_TMCFG0_NATHRD 0x00003f00 /* Number of active threads */
567#define TMRN_TMCFG0_NATHRD_SHIFT 8
568#define TMRN_TMCFG0_NTHRD 0x0000003f /* Number of threads */
569#define TMRN_IMSR0 0x120 /* Initial MSR Register 0 (e6500) */
570#define TMRN_IMSR1 0x121 /* Initial MSR Register 1 (e6500) */
571#define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */
572#define TMRN_INIA1 0x141 /* Next Instruction Address Register 1 */
573#define SPRN_TENSR 0x1b5 /* Thread Enable Status Register */
574#define SPRN_TENS 0x1b6 /* Thread Enable Set Register */
575#define SPRN_TENC 0x1b7 /* Thread Enable Clear Register */
576
577#define TEN_THREAD(x) (1 << (x))
578
579#ifndef __ASSEMBLY__
580#define mftmr(rn) ({unsigned long rval; \
581 asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
582#define mttmr(rn, v) asm volatile(MTTMR(rn, %0) : \
583 : "r" ((unsigned long)(v)) \
584 : "memory")
585
586extern unsigned long global_dbcr0[];
587
588#endif /* !__ASSEMBLY__ */
589
590#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
591#endif /* __KERNEL__ */