tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ9574 SoC device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8
9#include <dt-bindings/clock/qcom,apss-ipq.h>
10#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
11#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
12#include <dt-bindings/interconnect/qcom,ipq9574.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 clocks {
23 ref_48mhz_clk: ref-48mhz-clk {
24 compatible = "fixed-factor-clock";
25 clocks = <&xo_clk>;
26 #clock-cells = <0>;
27 };
28
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 };
33
34 xo_board_clk: xo-board-clk {
35 compatible = "fixed-factor-clock";
36 clocks = <&ref_48mhz_clk>;
37 #clock-cells = <0>;
38 };
39
40 xo_clk: xo-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 };
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a73";
53 reg = <0x0>;
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu";
58 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>;
61 };
62
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a73";
66 reg = <0x1>;
67 enable-method = "psci";
68 next-level-cache = <&l2_0>;
69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu";
71 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>;
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a73";
79 reg = <0x2>;
80 enable-method = "psci";
81 next-level-cache = <&l2_0>;
82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu";
84 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>;
87 };
88
89 cpu3: cpu@3 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a73";
92 reg = <0x3>;
93 enable-method = "psci";
94 next-level-cache = <&l2_0>;
95 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
96 clock-names = "cpu";
97 operating-points-v2 = <&cpu_opp_table>;
98 cpu-supply = <&ipq9574_s1>;
99 #cooling-cells = <2>;
100 };
101
102 l2_0: l2-cache {
103 compatible = "cache";
104 cache-level = <2>;
105 cache-unified;
106 };
107 };
108
109 firmware {
110 scm {
111 compatible = "qcom,scm-ipq9574", "qcom,scm";
112 qcom,dload-mode = <&tcsr 0x6100>;
113 };
114 };
115
116 memory@40000000 {
117 device_type = "memory";
118 /* We expect the bootloader to fill in the size */
119 reg = <0x0 0x40000000 0x0 0x0>;
120 };
121
122 cpu_opp_table: opp-table-cpu {
123 compatible = "operating-points-v2-kryo-cpu";
124 opp-shared;
125 nvmem-cells = <&cpu_speed_bin>;
126
127 opp-936000000 {
128 opp-hz = /bits/ 64 <936000000>;
129 opp-microvolt = <725000>;
130 opp-supported-hw = <0xf>;
131 clock-latency-ns = <200000>;
132 };
133
134 opp-1104000000 {
135 opp-hz = /bits/ 64 <1104000000>;
136 opp-microvolt = <787500>;
137 opp-supported-hw = <0xf>;
138 clock-latency-ns = <200000>;
139 };
140
141 opp-1200000000 {
142 opp-hz = /bits/ 64 <1200000000>;
143 opp-microvolt = <862500>;
144 opp-supported-hw = <0xf>;
145 clock-latency-ns = <200000>;
146 };
147
148 opp-1416000000 {
149 opp-hz = /bits/ 64 <1416000000>;
150 opp-microvolt = <862500>;
151 opp-supported-hw = <0x7>;
152 clock-latency-ns = <200000>;
153 };
154
155 opp-1488000000 {
156 opp-hz = /bits/ 64 <1488000000>;
157 opp-microvolt = <925000>;
158 opp-supported-hw = <0x7>;
159 clock-latency-ns = <200000>;
160 };
161
162 opp-1800000000 {
163 opp-hz = /bits/ 64 <1800000000>;
164 opp-microvolt = <987500>;
165 opp-supported-hw = <0x5>;
166 clock-latency-ns = <200000>;
167 };
168
169 opp-2208000000 {
170 opp-hz = /bits/ 64 <2208000000>;
171 opp-microvolt = <1062500>;
172 opp-supported-hw = <0x1>;
173 clock-latency-ns = <200000>;
174 };
175 };
176
177 pmu {
178 compatible = "arm,cortex-a73-pmu";
179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
180 };
181
182 psci {
183 compatible = "arm,psci-1.0";
184 method = "smc";
185 };
186
187 rpm: remoteproc {
188 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
189
190 glink-edge {
191 compatible = "qcom,glink-rpm";
192 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
193 qcom,rpm-msg-ram = <&rpm_msg_ram>;
194 mboxes = <&apcs_glb 0>;
195
196 rpm_requests: rpm-requests {
197 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
198 qcom,glink-channels = "rpm_requests";
199 };
200 };
201 };
202
203 reserved-memory {
204 #address-cells = <2>;
205 #size-cells = <2>;
206 ranges;
207
208 bootloader@4a100000 {
209 reg = <0x0 0x4a100000 0x0 0x400000>;
210 no-map;
211 };
212
213 sbl@4a500000 {
214 reg = <0x0 0x4a500000 0x0 0x100000>;
215 no-map;
216 };
217
218 tz_region: tz@4a600000 {
219 reg = <0x0 0x4a600000 0x0 0x400000>;
220 no-map;
221 };
222
223 smem@4aa00000 {
224 compatible = "qcom,smem";
225 reg = <0x0 0x4aa00000 0x0 0x100000>;
226 hwlocks = <&tcsr_mutex 3>;
227 no-map;
228 };
229 };
230
231 soc: soc@0 {
232 compatible = "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 ranges = <0 0 0 0xffffffff>;
236
237 rpm_msg_ram: sram@60000 {
238 compatible = "qcom,rpm-msg-ram";
239 reg = <0x00060000 0x6000>;
240 };
241
242 pcie0_phy: phy@84000 {
243 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
244 reg = <0x00084000 0x1000>;
245
246 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
247 <&gcc GCC_PCIE0_AHB_CLK>,
248 <&gcc GCC_PCIE0_PIPE_CLK>;
249 clock-names = "aux", "cfg_ahb", "pipe";
250
251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
252 assigned-clock-rates = <20000000>;
253
254 resets = <&gcc GCC_PCIE0_PHY_BCR>,
255 <&gcc GCC_PCIE0PHY_PHY_BCR>;
256 reset-names = "phy", "common";
257
258 #clock-cells = <0>;
259 clock-output-names = "gcc_pcie0_pipe_clk_src";
260
261 #phy-cells = <0>;
262 status = "disabled";
263 };
264
265 pcie2_phy: phy@8c000 {
266 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
267 reg = <0x0008c000 0x2000>;
268
269 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
270 <&gcc GCC_PCIE2_AHB_CLK>,
271 <&gcc GCC_PCIE2_PIPE_CLK>;
272 clock-names = "aux", "cfg_ahb", "pipe";
273
274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
275 assigned-clock-rates = <20000000>;
276
277 resets = <&gcc GCC_PCIE2_PHY_BCR>,
278 <&gcc GCC_PCIE2PHY_PHY_BCR>;
279 reset-names = "phy", "common";
280
281 #clock-cells = <0>;
282 clock-output-names = "gcc_pcie2_pipe_clk_src";
283
284 #phy-cells = <0>;
285 status = "disabled";
286 };
287
288 rng: rng@e3000 {
289 compatible = "qcom,ipq9574-trng", "qcom,trng";
290 reg = <0x000e3000 0x1000>;
291 clocks = <&gcc GCC_PRNG_AHB_CLK>;
292 clock-names = "core";
293 };
294
295 mdio: mdio@90000 {
296 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
297 reg = <0x00090000 0x64>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 clocks = <&gcc GCC_MDIO_AHB_CLK>;
301 clock-names = "gcc_mdio_ahb_clk";
302 status = "disabled";
303 };
304
305 pcie3_phy: phy@f4000 {
306 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
307 reg = <0x000f4000 0x2000>;
308
309 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
310 <&gcc GCC_PCIE3_AHB_CLK>,
311 <&gcc GCC_PCIE3_PIPE_CLK>;
312 clock-names = "aux", "cfg_ahb", "pipe";
313
314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
315 assigned-clock-rates = <20000000>;
316
317 resets = <&gcc GCC_PCIE3_PHY_BCR>,
318 <&gcc GCC_PCIE3PHY_PHY_BCR>;
319 reset-names = "phy", "common";
320
321 #clock-cells = <0>;
322 clock-output-names = "gcc_pcie3_pipe_clk_src";
323
324 #phy-cells = <0>;
325 status = "disabled";
326 };
327
328 pcie1_phy: phy@fc000 {
329 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
330 reg = <0x000fc000 0x1000>;
331
332 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
333 <&gcc GCC_PCIE1_AHB_CLK>,
334 <&gcc GCC_PCIE1_PIPE_CLK>;
335 clock-names = "aux", "cfg_ahb", "pipe";
336
337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
338 assigned-clock-rates = <20000000>;
339
340 resets = <&gcc GCC_PCIE1_PHY_BCR>,
341 <&gcc GCC_PCIE1PHY_PHY_BCR>;
342 reset-names = "phy", "common";
343
344 #clock-cells = <0>;
345 clock-output-names = "gcc_pcie1_pipe_clk_src";
346
347 #phy-cells = <0>;
348 status = "disabled";
349 };
350
351 cmn_pll: clock-controller@9b000 {
352 compatible = "qcom,ipq9574-cmn-pll";
353 reg = <0x0009b000 0x800>;
354 clocks = <&ref_48mhz_clk>,
355 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
356 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
357 clock-names = "ref", "ahb", "sys";
358 #clock-cells = <1>;
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
360 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
361 };
362
363 qfprom: efuse@a4000 {
364 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
365 reg = <0x000a4000 0x5a1>;
366 #address-cells = <1>;
367 #size-cells = <1>;
368
369 cpu_speed_bin: cpu-speed-bin@15 {
370 reg = <0x15 0x2>;
371 bits = <7 2>;
372 };
373 };
374
375 cryptobam: dma-controller@704000 {
376 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
377 reg = <0x00704000 0x20000>;
378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
379 #dma-cells = <1>;
380 qcom,ee = <1>;
381 qcom,controlled-remotely;
382 };
383
384 crypto: crypto@73a000 {
385 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
386 reg = <0x0073a000 0x6000>;
387 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
388 <&gcc GCC_CRYPTO_AXI_CLK>,
389 <&gcc GCC_CRYPTO_CLK>;
390 clock-names = "iface", "bus", "core";
391 dmas = <&cryptobam 2>, <&cryptobam 3>;
392 dma-names = "rx", "tx";
393 };
394
395 tsens: thermal-sensor@4a9000 {
396 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
397 reg = <0x004a9000 0x1000>,
398 <0x004a8000 0x1000>;
399 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
400 interrupt-names = "combined";
401 #qcom,sensors = <16>;
402 #thermal-sensor-cells = <1>;
403 };
404
405 tlmm: pinctrl@1000000 {
406 compatible = "qcom,ipq9574-tlmm";
407 reg = <0x01000000 0x300000>;
408 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 gpio-ranges = <&tlmm 0 0 65>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414
415 uart2_pins: uart2-state {
416 pins = "gpio34", "gpio35";
417 function = "blsp2_uart";
418 drive-strength = <8>;
419 bias-disable;
420 };
421 };
422
423 gcc: clock-controller@1800000 {
424 compatible = "qcom,ipq9574-gcc";
425 reg = <0x01800000 0x80000>;
426 clocks = <&xo_board_clk>,
427 <&sleep_clk>,
428 <0>,
429 <&pcie0_phy>,
430 <&pcie1_phy>,
431 <&pcie2_phy>,
432 <&pcie3_phy>,
433 <0>;
434 #clock-cells = <1>;
435 #reset-cells = <1>;
436 #interconnect-cells = <1>;
437 };
438
439 tcsr_mutex: hwlock@1905000 {
440 compatible = "qcom,tcsr-mutex";
441 reg = <0x01905000 0x20000>;
442 #hwlock-cells = <1>;
443 };
444
445 tcsr: syscon@1937000 {
446 compatible = "qcom,tcsr-ipq9574", "syscon";
447 reg = <0x01937000 0x21000>;
448 };
449
450 sdhc_1: mmc@7804000 {
451 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
452 reg = <0x07804000 0x1000>,
453 <0x07805000 0x1000>,
454 <0x07808000 0x2000>;
455 reg-names = "hc", "cqhci", "ice";
456
457 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "hc_irq", "pwr_irq";
460
461 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
462 <&gcc GCC_SDCC1_APPS_CLK>,
463 <&xo_board_clk>,
464 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
465 clock-names = "iface", "core", "xo", "ice";
466 non-removable;
467 supports-cqe;
468 status = "disabled";
469 };
470
471 blsp_dma: dma-controller@7884000 {
472 compatible = "qcom,bam-v1.7.0";
473 reg = <0x07884000 0x2b000>;
474 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "bam_clk";
477 #dma-cells = <1>;
478 qcom,ee = <0>;
479 };
480
481 blsp1_uart0: serial@78af000 {
482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
483 reg = <0x078af000 0x200>;
484 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
486 <&gcc GCC_BLSP1_AHB_CLK>;
487 clock-names = "core", "iface";
488 status = "disabled";
489 };
490
491 blsp1_uart1: serial@78b0000 {
492 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
493 reg = <0x078b0000 0x200>;
494 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
496 <&gcc GCC_BLSP1_AHB_CLK>;
497 clock-names = "core", "iface";
498 status = "disabled";
499 };
500
501 blsp1_uart2: serial@78b1000 {
502 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
503 reg = <0x078b1000 0x200>;
504 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
506 <&gcc GCC_BLSP1_AHB_CLK>;
507 clock-names = "core", "iface";
508 status = "disabled";
509 };
510
511 blsp1_uart3: serial@78b2000 {
512 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
513 reg = <0x078b2000 0x200>;
514 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
516 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", "iface";
518 status = "disabled";
519 };
520
521 blsp1_uart4: serial@78b3000 {
522 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
523 reg = <0x078b3000 0x200>;
524 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
526 <&gcc GCC_BLSP1_AHB_CLK>;
527 clock-names = "core", "iface";
528 status = "disabled";
529 };
530
531 blsp1_uart5: serial@78b4000 {
532 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
533 reg = <0x078b4000 0x200>;
534 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
536 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", "iface";
538 status = "disabled";
539 };
540
541 blsp1_spi0: spi@78b5000 {
542 compatible = "qcom,spi-qup-v2.2.1";
543 reg = <0x078b5000 0x600>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
550 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
551 dma-names = "tx", "rx";
552 status = "disabled";
553 };
554
555 blsp1_i2c1: i2c@78b6000 {
556 compatible = "qcom,i2c-qup-v2.2.1";
557 reg = <0x078b6000 0x600>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", "iface";
564 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
565 assigned-clock-rates = <50000000>;
566 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
567 dma-names = "tx", "rx";
568 status = "disabled";
569 };
570
571 blsp1_spi1: spi@78b6000 {
572 compatible = "qcom,spi-qup-v2.2.1";
573 reg = <0x078b6000 0x600>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
578 <&gcc GCC_BLSP1_AHB_CLK>;
579 clock-names = "core", "iface";
580 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
581 dma-names = "tx", "rx";
582 status = "disabled";
583 };
584
585 blsp1_i2c2: i2c@78b7000 {
586 compatible = "qcom,i2c-qup-v2.2.1";
587 reg = <0x078b7000 0x600>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
592 <&gcc GCC_BLSP1_AHB_CLK>;
593 clock-names = "core", "iface";
594 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
595 assigned-clock-rates = <50000000>;
596 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
597 dma-names = "tx", "rx";
598 status = "disabled";
599 };
600
601 blsp1_spi2: spi@78b7000 {
602 compatible = "qcom,spi-qup-v2.2.1";
603 reg = <0x078b7000 0x600>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
608 <&gcc GCC_BLSP1_AHB_CLK>;
609 clock-names = "core", "iface";
610 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
611 dma-names = "tx", "rx";
612 status = "disabled";
613 };
614
615 blsp1_i2c3: i2c@78b8000 {
616 compatible = "qcom,i2c-qup-v2.2.1";
617 reg = <0x078b8000 0x600>;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
622 <&gcc GCC_BLSP1_AHB_CLK>;
623 clock-names = "core", "iface";
624 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
625 assigned-clock-rates = <50000000>;
626 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
627 dma-names = "tx", "rx";
628 status = "disabled";
629 };
630
631 blsp1_spi3: spi@78b8000 {
632 compatible = "qcom,spi-qup-v2.2.1";
633 reg = <0x078b8000 0x600>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
637 spi-max-frequency = <50000000>;
638 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
639 <&gcc GCC_BLSP1_AHB_CLK>;
640 clock-names = "core", "iface";
641 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
642 dma-names = "tx", "rx";
643 status = "disabled";
644 };
645
646 blsp1_i2c4: i2c@78b9000 {
647 compatible = "qcom,i2c-qup-v2.2.1";
648 reg = <0x078b9000 0x600>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
653 <&gcc GCC_BLSP1_AHB_CLK>;
654 clock-names = "core", "iface";
655 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
656 assigned-clock-rates = <50000000>;
657 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
658 dma-names = "tx", "rx";
659 status = "disabled";
660 };
661
662 blsp1_spi4: spi@78b9000 {
663 compatible = "qcom,spi-qup-v2.2.1";
664 reg = <0x078b9000 0x600>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
669 <&gcc GCC_BLSP1_AHB_CLK>;
670 clock-names = "core", "iface";
671 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
672 dma-names = "tx", "rx";
673 status = "disabled";
674 };
675
676 usb_0_qusbphy: phy@7b000 {
677 compatible = "qcom,ipq9574-qusb2-phy";
678 reg = <0x0007b000 0x180>;
679 #phy-cells = <0>;
680
681 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
682 <&xo_board_clk>;
683 clock-names = "cfg_ahb",
684 "ref";
685
686 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
687 status = "disabled";
688 };
689
690 usb_0_qmpphy: phy@7d000 {
691 compatible = "qcom,ipq9574-qmp-usb3-phy";
692 reg = <0x0007d000 0xa00>;
693 #phy-cells = <0>;
694
695 clocks = <&gcc GCC_USB0_AUX_CLK>,
696 <&xo_board_clk>,
697 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
698 <&gcc GCC_USB0_PIPE_CLK>;
699 clock-names = "aux",
700 "ref",
701 "cfg_ahb",
702 "pipe";
703
704 resets = <&gcc GCC_USB0_PHY_BCR>,
705 <&gcc GCC_USB3PHY_0_PHY_BCR>;
706 reset-names = "phy",
707 "phy_phy";
708
709 #clock-cells = <0>;
710 clock-output-names = "usb0_pipe_clk";
711
712 status = "disabled";
713 };
714
715 usb3: usb@8af8800 {
716 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
717 reg = <0x08af8800 0x400>;
718 #address-cells = <1>;
719 #size-cells = <1>;
720 ranges;
721
722 clocks = <&gcc GCC_SNOC_USB_CLK>,
723 <&gcc GCC_USB0_MASTER_CLK>,
724 <&gcc GCC_ANOC_USB_AXI_CLK>,
725 <&gcc GCC_USB0_SLEEP_CLK>,
726 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
727
728 clock-names = "cfg_noc",
729 "core",
730 "iface",
731 "sleep",
732 "mock_utmi";
733
734 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
735 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
736 assigned-clock-rates = <200000000>,
737 <24000000>;
738
739 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
740 interrupt-names = "pwr_event";
741
742 resets = <&gcc GCC_USB_BCR>;
743 status = "disabled";
744
745 usb_0_dwc3: usb@8a00000 {
746 compatible = "snps,dwc3";
747 reg = <0x8a00000 0xcd00>;
748 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
749 clock-names = "ref";
750 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
751 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
752 phy-names = "usb2-phy", "usb3-phy";
753 tx-fifo-resize;
754 snps,is-utmi-l1-suspend;
755 snps,hird-threshold = /bits/ 8 <0x0>;
756 snps,dis_u2_susphy_quirk;
757 snps,dis_u3_susphy_quirk;
758 };
759 };
760
761 intc: interrupt-controller@b000000 {
762 compatible = "qcom,msm-qgic2";
763 reg = <0x0b000000 0x1000>, /* GICD */
764 <0x0b002000 0x2000>, /* GICC */
765 <0x0b001000 0x1000>, /* GICH */
766 <0x0b004000 0x2000>; /* GICV */
767 #address-cells = <1>;
768 #size-cells = <1>;
769 interrupt-controller;
770 #interrupt-cells = <3>;
771 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
772 ranges = <0 0x0b00c000 0x3000>;
773
774 v2m0: v2m@0 {
775 compatible = "arm,gic-v2m-frame";
776 reg = <0x00000000 0xffd>;
777 msi-controller;
778 };
779
780 v2m1: v2m@1000 {
781 compatible = "arm,gic-v2m-frame";
782 reg = <0x00001000 0xffd>;
783 msi-controller;
784 };
785
786 v2m2: v2m@2000 {
787 compatible = "arm,gic-v2m-frame";
788 reg = <0x00002000 0xffd>;
789 msi-controller;
790 };
791 };
792
793 watchdog: watchdog@b017000 {
794 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
795 reg = <0x0b017000 0x1000>;
796 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
797 clocks = <&sleep_clk>;
798 timeout-sec = <30>;
799 };
800
801 apcs_glb: mailbox@b111000 {
802 compatible = "qcom,ipq9574-apcs-apps-global",
803 "qcom,ipq6018-apcs-apps-global";
804 reg = <0x0b111000 0x1000>;
805 #clock-cells = <1>;
806 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
807 clock-names = "pll", "xo", "gpll0";
808 #mbox-cells = <1>;
809 };
810
811 a73pll: clock@b116000 {
812 compatible = "qcom,ipq9574-a73pll";
813 reg = <0x0b116000 0x40>;
814 #clock-cells = <0>;
815 clocks = <&xo_board_clk>;
816 clock-names = "xo";
817 };
818
819 timer@b120000 {
820 compatible = "arm,armv7-timer-mem";
821 reg = <0x0b120000 0x1000>;
822 #address-cells = <1>;
823 #size-cells = <1>;
824 ranges;
825
826 frame@b120000 {
827 reg = <0x0b121000 0x1000>,
828 <0x0b122000 0x1000>;
829 frame-number = <0>;
830 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
832 };
833
834 frame@b123000 {
835 reg = <0x0b123000 0x1000>;
836 frame-number = <1>;
837 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
838 status = "disabled";
839 };
840
841 frame@b124000 {
842 reg = <0x0b124000 0x1000>;
843 frame-number = <2>;
844 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
845 status = "disabled";
846 };
847
848 frame@b125000 {
849 reg = <0x0b125000 0x1000>;
850 frame-number = <3>;
851 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
852 status = "disabled";
853 };
854
855 frame@b126000 {
856 reg = <0x0b126000 0x1000>;
857 frame-number = <4>;
858 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
859 status = "disabled";
860 };
861
862 frame@b127000 {
863 reg = <0x0b127000 0x1000>;
864 frame-number = <5>;
865 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
866 status = "disabled";
867 };
868
869 frame@b128000 {
870 reg = <0x0b128000 0x1000>;
871 frame-number = <6>;
872 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
873 status = "disabled";
874 };
875 };
876
877 pcie1: pcie@10000000 {
878 compatible = "qcom,pcie-ipq9574";
879 reg = <0x10000000 0xf1d>,
880 <0x10000f20 0xa8>,
881 <0x10001000 0x1000>,
882 <0x000f8000 0x4000>,
883 <0x10100000 0x1000>;
884 reg-names = "dbi", "elbi", "atu", "parf", "config";
885 device_type = "pci";
886 linux,pci-domain = <1>;
887 bus-range = <0x00 0xff>;
888 num-lanes = <1>;
889 #address-cells = <3>;
890 #size-cells = <2>;
891
892 ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
893 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
894
895 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "msi0",
904 "msi1",
905 "msi2",
906 "msi3",
907 "msi4",
908 "msi5",
909 "msi6",
910 "msi7";
911
912 #interrupt-cells = <1>;
913 interrupt-map-mask = <0 0 0 0x7>;
914 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
915 <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
916 <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
917 <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
918
919 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
920 <&gcc GCC_PCIE1_AXI_S_CLK>,
921 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
922 <&gcc GCC_PCIE1_RCHNG_CLK>,
923 <&gcc GCC_PCIE1_AHB_CLK>,
924 <&gcc GCC_PCIE1_AUX_CLK>;
925 clock-names = "axi_m",
926 "axi_s",
927 "axi_bridge",
928 "rchng",
929 "ahb",
930 "aux";
931
932 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
933 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
934 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
935 <&gcc GCC_PCIE1_AXI_S_ARES>,
936 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
937 <&gcc GCC_PCIE1_AXI_M_ARES>,
938 <&gcc GCC_PCIE1_AUX_ARES>,
939 <&gcc GCC_PCIE1_AHB_ARES>;
940 reset-names = "pipe",
941 "sticky",
942 "axi_s_sticky",
943 "axi_s",
944 "axi_m_sticky",
945 "axi_m",
946 "aux",
947 "ahb";
948
949 phys = <&pcie1_phy>;
950 phy-names = "pciephy";
951 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
952 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
953 interconnect-names = "pcie-mem", "cpu-pcie";
954 status = "disabled";
955 };
956
957 pcie3: pcie@18000000 {
958 compatible = "qcom,pcie-ipq9574";
959 reg = <0x18000000 0xf1d>,
960 <0x18000f20 0xa8>,
961 <0x18001000 0x1000>,
962 <0x000f0000 0x4000>,
963 <0x18100000 0x1000>;
964 reg-names = "dbi", "elbi", "atu", "parf", "config";
965 device_type = "pci";
966 linux,pci-domain = <3>;
967 bus-range = <0x00 0xff>;
968 num-lanes = <2>;
969 #address-cells = <3>;
970 #size-cells = <2>;
971
972 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
973 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
974
975 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
983 interrupt-names = "msi0",
984 "msi1",
985 "msi2",
986 "msi3",
987 "msi4",
988 "msi5",
989 "msi6",
990 "msi7";
991
992 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0 0 0x7>;
994 interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
995 <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
996 <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
997 <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
998
999 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
1000 <&gcc GCC_PCIE3_AXI_S_CLK>,
1001 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
1002 <&gcc GCC_PCIE3_RCHNG_CLK>,
1003 <&gcc GCC_PCIE3_AHB_CLK>,
1004 <&gcc GCC_PCIE3_AUX_CLK>;
1005 clock-names = "axi_m",
1006 "axi_s",
1007 "axi_bridge",
1008 "rchng",
1009 "ahb",
1010 "aux";
1011
1012 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
1013 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
1014 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
1015 <&gcc GCC_PCIE3_AXI_S_ARES>,
1016 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
1017 <&gcc GCC_PCIE3_AXI_M_ARES>,
1018 <&gcc GCC_PCIE3_AUX_ARES>,
1019 <&gcc GCC_PCIE3_AHB_ARES>;
1020 reset-names = "pipe",
1021 "sticky",
1022 "axi_s_sticky",
1023 "axi_s",
1024 "axi_m_sticky",
1025 "axi_m",
1026 "aux",
1027 "ahb";
1028
1029 phys = <&pcie3_phy>;
1030 phy-names = "pciephy";
1031 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
1032 <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
1033 interconnect-names = "pcie-mem", "cpu-pcie";
1034 status = "disabled";
1035 };
1036
1037 pcie2: pcie@20000000 {
1038 compatible = "qcom,pcie-ipq9574";
1039 reg = <0x20000000 0xf1d>,
1040 <0x20000f20 0xa8>,
1041 <0x20001000 0x1000>,
1042 <0x00088000 0x4000>,
1043 <0x20100000 0x1000>;
1044 reg-names = "dbi", "elbi", "atu", "parf", "config";
1045 device_type = "pci";
1046 linux,pci-domain = <2>;
1047 bus-range = <0x00 0xff>;
1048 num-lanes = <2>;
1049 #address-cells = <3>;
1050 #size-cells = <2>;
1051
1052 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
1053 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
1054
1055 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1063 interrupt-names = "msi0",
1064 "msi1",
1065 "msi2",
1066 "msi3",
1067 "msi4",
1068 "msi5",
1069 "msi6",
1070 "msi7";
1071
1072 #interrupt-cells = <1>;
1073 interrupt-map-mask = <0 0 0 0x7>;
1074 interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
1075 <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
1076 <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
1077 <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
1078
1079 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
1080 <&gcc GCC_PCIE2_AXI_S_CLK>,
1081 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
1082 <&gcc GCC_PCIE2_RCHNG_CLK>,
1083 <&gcc GCC_PCIE2_AHB_CLK>,
1084 <&gcc GCC_PCIE2_AUX_CLK>;
1085 clock-names = "axi_m",
1086 "axi_s",
1087 "axi_bridge",
1088 "rchng",
1089 "ahb",
1090 "aux";
1091
1092 resets = <&gcc GCC_PCIE2_PIPE_ARES>,
1093 <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
1094 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
1095 <&gcc GCC_PCIE2_AXI_S_ARES>,
1096 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
1097 <&gcc GCC_PCIE2_AXI_M_ARES>,
1098 <&gcc GCC_PCIE2_AUX_ARES>,
1099 <&gcc GCC_PCIE2_AHB_ARES>;
1100 reset-names = "pipe",
1101 "sticky",
1102 "axi_s_sticky",
1103 "axi_s",
1104 "axi_m_sticky",
1105 "axi_m",
1106 "aux",
1107 "ahb";
1108
1109 phys = <&pcie2_phy>;
1110 phy-names = "pciephy";
1111 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
1112 <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
1113 interconnect-names = "pcie-mem", "cpu-pcie";
1114 status = "disabled";
1115 };
1116
1117 pcie0: pci@28000000 {
1118 compatible = "qcom,pcie-ipq9574";
1119 reg = <0x28000000 0xf1d>,
1120 <0x28000f20 0xa8>,
1121 <0x28001000 0x1000>,
1122 <0x00080000 0x4000>,
1123 <0x28100000 0x1000>;
1124 reg-names = "dbi", "elbi", "atu", "parf", "config";
1125 device_type = "pci";
1126 linux,pci-domain = <0>;
1127 bus-range = <0x00 0xff>;
1128 num-lanes = <1>;
1129 #address-cells = <3>;
1130 #size-cells = <2>;
1131
1132 ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
1133 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
1134 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1142 interrupt-names = "msi0",
1143 "msi1",
1144 "msi2",
1145 "msi3",
1146 "msi4",
1147 "msi5",
1148 "msi6",
1149 "msi7";
1150
1151 #interrupt-cells = <1>;
1152 interrupt-map-mask = <0 0 0 0x7>;
1153 interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
1154 <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
1155 <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
1156 <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
1157
1158 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
1159 <&gcc GCC_PCIE0_AXI_S_CLK>,
1160 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
1161 <&gcc GCC_PCIE0_RCHNG_CLK>,
1162 <&gcc GCC_PCIE0_AHB_CLK>,
1163 <&gcc GCC_PCIE0_AUX_CLK>;
1164 clock-names = "axi_m",
1165 "axi_s",
1166 "axi_bridge",
1167 "rchng",
1168 "ahb",
1169 "aux";
1170
1171 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
1172 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
1173 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
1174 <&gcc GCC_PCIE0_AXI_S_ARES>,
1175 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
1176 <&gcc GCC_PCIE0_AXI_M_ARES>,
1177 <&gcc GCC_PCIE0_AUX_ARES>,
1178 <&gcc GCC_PCIE0_AHB_ARES>;
1179 reset-names = "pipe",
1180 "sticky",
1181 "axi_s_sticky",
1182 "axi_s",
1183 "axi_m_sticky",
1184 "axi_m",
1185 "aux",
1186 "ahb";
1187
1188 phys = <&pcie0_phy>;
1189 phy-names = "pciephy";
1190 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
1191 <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
1192 interconnect-names = "pcie-mem", "cpu-pcie";
1193 status = "disabled";
1194 };
1195
1196 };
1197
1198 thermal-zones {
1199 nss-top-thermal {
1200 thermal-sensors = <&tsens 3>;
1201
1202 trips {
1203 nss-top-critical {
1204 temperature = <125000>;
1205 hysteresis = <1000>;
1206 type = "critical";
1207 };
1208 };
1209 };
1210
1211 ubi-0-thermal {
1212 thermal-sensors = <&tsens 4>;
1213
1214 trips {
1215 ubi_0-critical {
1216 temperature = <125000>;
1217 hysteresis = <1000>;
1218 type = "critical";
1219 };
1220 };
1221 };
1222
1223 ubi-1-thermal {
1224 thermal-sensors = <&tsens 5>;
1225
1226 trips {
1227 ubi_1-critical {
1228 temperature = <125000>;
1229 hysteresis = <1000>;
1230 type = "critical";
1231 };
1232 };
1233 };
1234
1235 ubi-2-thermal {
1236 thermal-sensors = <&tsens 6>;
1237
1238 trips {
1239 ubi_2-critical {
1240 temperature = <125000>;
1241 hysteresis = <1000>;
1242 type = "critical";
1243 };
1244 };
1245 };
1246
1247 ubi-3-thermal {
1248 thermal-sensors = <&tsens 7>;
1249
1250 trips {
1251 ubi_3-critical {
1252 temperature = <125000>;
1253 hysteresis = <1000>;
1254 type = "critical";
1255 };
1256 };
1257 };
1258
1259 cpuss0-thermal {
1260 thermal-sensors = <&tsens 8>;
1261
1262 trips {
1263 cpu-critical {
1264 temperature = <125000>;
1265 hysteresis = <1000>;
1266 type = "critical";
1267 };
1268 };
1269 };
1270
1271 cpuss1-thermal {
1272 thermal-sensors = <&tsens 9>;
1273
1274 trips {
1275 cpu-critical {
1276 temperature = <125000>;
1277 hysteresis = <1000>;
1278 type = "critical";
1279 };
1280 };
1281 };
1282
1283 cpu0-thermal {
1284 thermal-sensors = <&tsens 10>;
1285
1286 trips {
1287 cpu0_crit: cpu-critical {
1288 temperature = <120000>;
1289 hysteresis = <10000>;
1290 type = "critical";
1291 };
1292
1293 cpu0_alert: cpu-passive {
1294 temperature = <110000>;
1295 hysteresis = <1000>;
1296 type = "passive";
1297 };
1298 };
1299
1300 cooling-maps {
1301 map0 {
1302 trip = <&cpu0_alert>;
1303 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1304 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1305 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1306 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1307 };
1308 };
1309 };
1310
1311 cpu1-thermal {
1312 thermal-sensors = <&tsens 11>;
1313
1314 trips {
1315 cpu1_crit: cpu-critical {
1316 temperature = <120000>;
1317 hysteresis = <10000>;
1318 type = "critical";
1319 };
1320
1321 cpu1_alert: cpu-passive {
1322 temperature = <110000>;
1323 hysteresis = <1000>;
1324 type = "passive";
1325 };
1326 };
1327
1328 cooling-maps {
1329 map0 {
1330 trip = <&cpu1_alert>;
1331 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1332 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1333 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1334 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1335 };
1336 };
1337 };
1338
1339 cpu2-thermal {
1340 thermal-sensors = <&tsens 12>;
1341
1342 trips {
1343 cpu2_crit: cpu-critical {
1344 temperature = <120000>;
1345 hysteresis = <10000>;
1346 type = "critical";
1347 };
1348
1349 cpu2_alert: cpu-passive {
1350 temperature = <110000>;
1351 hysteresis = <1000>;
1352 type = "passive";
1353 };
1354 };
1355
1356 cooling-maps {
1357 map0 {
1358 trip = <&cpu2_alert>;
1359 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1360 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1361 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1362 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1363 };
1364 };
1365 };
1366
1367 cpu3-thermal {
1368 thermal-sensors = <&tsens 13>;
1369
1370 trips {
1371 cpu3_crit: cpu-critical {
1372 temperature = <120000>;
1373 hysteresis = <10000>;
1374 type = "critical";
1375 };
1376
1377 cpu3_alert: cpu-passive {
1378 temperature = <110000>;
1379 hysteresis = <1000>;
1380 type = "passive";
1381 };
1382 };
1383
1384 cooling-maps {
1385 map0 {
1386 trip = <&cpu3_alert>;
1387 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1388 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1389 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1390 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1391 };
1392 };
1393 };
1394
1395 wcss-phyb-thermal {
1396 thermal-sensors = <&tsens 14>;
1397
1398 trips {
1399 wcss_phyb-critical {
1400 temperature = <125000>;
1401 hysteresis = <1000>;
1402 type = "critical";
1403 };
1404 };
1405 };
1406
1407 top-glue-thermal {
1408 thermal-sensors = <&tsens 15>;
1409
1410 trips {
1411 top_glue-critical {
1412 temperature = <125000>;
1413 hysteresis = <1000>;
1414 type = "critical";
1415 };
1416 };
1417 };
1418 };
1419
1420 timer {
1421 compatible = "arm,armv8-timer";
1422 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1423 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1424 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1425 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1426 };
1427};