tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple S5L8960X "A7" SoC
4 *
5 * Other Names: H6, "Alcatraz"
6 *
7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/apple-aic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/pinctrl/apple.h>
15
16/ {
17 interrupt-parent = <&aic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 clkref: clock-ref {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24000000>;
25 clock-output-names = "clkref";
26 };
27
28 cpus {
29 #address-cells = <2>;
30 #size-cells = <0>;
31
32 cpu0: cpu@0 {
33 compatible = "apple,cyclone";
34 reg = <0x0 0x0>;
35 cpu-release-addr = <0 0>; /* To be filled by loader */
36 operating-points-v2 = <&cyclone_opp>;
37 performance-domains = <&cpufreq>;
38 enable-method = "spin-table";
39 device_type = "cpu";
40 };
41
42 cpu1: cpu@1 {
43 compatible = "apple,cyclone";
44 reg = <0x0 0x1>;
45 cpu-release-addr = <0 0>; /* To be filled by loader */
46 operating-points-v2 = <&cyclone_opp>;
47 performance-domains = <&cpufreq>;
48 enable-method = "spin-table";
49 device_type = "cpu";
50 };
51 };
52
53 soc {
54 compatible = "simple-bus";
55 #address-cells = <2>;
56 #size-cells = <2>;
57 nonposted-mmio;
58 ranges;
59
60 cpufreq: performance-controller@202220000 {
61 compatible = "apple,s5l8960x-cluster-cpufreq";
62 reg = <0x2 0x02220000 0 0x1000>;
63 #performance-domain-cells = <0>;
64 };
65
66 serial0: serial@20a0a0000 {
67 compatible = "apple,s5l-uart";
68 reg = <0x2 0x0a0a0000 0x0 0x4000>;
69 reg-io-width = <4>;
70 interrupt-parent = <&aic>;
71 interrupts = <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>;
72 /* Use the bootloader-enabled clocks for now. */
73 clocks = <&clkref>, <&clkref>;
74 clock-names = "uart", "clk_uart_baud0";
75 power-domains = <&ps_uart0>;
76 status = "disabled";
77 };
78
79 pmgr: power-management@20e000000 {
80 compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd";
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 reg = <0x2 0xe000000 0 0x24000>;
85 };
86
87 wdt: watchdog@20e027000 {
88 compatible = "apple,s5l8960x-wdt", "apple,wdt";
89 reg = <0x2 0x0e027000 0x0 0x1000>;
90 clocks = <&clkref>;
91 interrupt-parent = <&aic>;
92 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
93 };
94
95 aic: interrupt-controller@20e100000 {
96 compatible = "apple,s5l8960x-aic", "apple,aic";
97 reg = <0x2 0x0e100000 0x0 0x100000>;
98 #interrupt-cells = <3>;
99 interrupt-controller;
100 power-domains = <&ps_aic>;
101 };
102
103 dwi_bl: backlight@20e200010 {
104 compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl";
105 reg = <0x2 0x0e200010 0x0 0x8>;
106 power-domains = <&ps_dwi>;
107 status = "disabled";
108 };
109
110 pinctrl: pinctrl@20e300000 {
111 compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl";
112 reg = <0x2 0x0e300000 0x0 0x100000>;
113 power-domains = <&ps_gpio>;
114
115 gpio-controller;
116 #gpio-cells = <2>;
117 gpio-ranges = <&pinctrl 0 0 200>;
118 apple,npins = <200>;
119
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 interrupt-parent = <&aic>;
123 interrupts = <AIC_IRQ 108 IRQ_TYPE_LEVEL_HIGH>,
124 <AIC_IRQ 109 IRQ_TYPE_LEVEL_HIGH>,
125 <AIC_IRQ 110 IRQ_TYPE_LEVEL_HIGH>,
126 <AIC_IRQ 111 IRQ_TYPE_LEVEL_HIGH>,
127 <AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH>,
128 <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>,
129 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>;
130 };
131 };
132
133 timer {
134 compatible = "arm,armv8-timer";
135 interrupt-parent = <&aic>;
136 interrupt-names = "phys", "virt";
137 /* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */
138 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
139 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
140 };
141};
142
143#include "s5l8960x-pmgr.dtsi"