tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
8
9maintainers:
10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
11
12properties:
13 compatible:
14 oneOf:
15 - enum:
16 - rockchip,rk3588-hdptx-phy
17 - items:
18 - enum:
19 - rockchip,rk3576-hdptx-phy
20 - const: rockchip,rk3588-hdptx-phy
21
22 reg:
23 maxItems: 1
24
25 clocks:
26 items:
27 - description: Reference clock
28 - description: APB clock
29
30 clock-names:
31 items:
32 - const: ref
33 - const: apb
34
35 "#clock-cells":
36 const: 0
37
38 "#phy-cells":
39 const: 0
40
41 resets:
42 minItems: 4
43 maxItems: 7
44
45 reset-names:
46 minItems: 4
47 maxItems: 7
48
49 rockchip,grf:
50 $ref: /schemas/types.yaml#/definitions/phandle
51 description: Some PHY related data is accessed through GRF regs.
52
53required:
54 - compatible
55 - reg
56 - clocks
57 - clock-names
58 - "#phy-cells"
59 - resets
60 - reset-names
61 - rockchip,grf
62
63allOf:
64 - if:
65 properties:
66 compatible:
67 contains:
68 enum:
69 - rockchip,rk3576-hdptx-phy
70 then:
71 properties:
72 resets:
73 minItems: 4
74 maxItems: 4
75 reset-names:
76 items:
77 - const: apb
78 - const: init
79 - const: cmn
80 - const: lane
81 else:
82 properties:
83 resets:
84 minItems: 7
85 maxItems: 7
86 reset-names:
87 items:
88 - const: phy
89 - const: apb
90 - const: init
91 - const: cmn
92 - const: lane
93 - const: ropll
94 - const: lcpll
95
96additionalProperties: false
97
98examples:
99 - |
100 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
101 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
102
103 soc {
104 #address-cells = <2>;
105 #size-cells = <2>;
106
107 phy@fed60000 {
108 compatible = "rockchip,rk3588-hdptx-phy";
109 reg = <0x0 0xfed60000 0x0 0x2000>;
110 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
111 clock-names = "ref", "apb";
112 #phy-cells = <0>;
113 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
114 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
115 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
116 <&cru SRST_HDPTX0_LCPLL>;
117 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
118 rockchip,grf = <&hdptxphy_grf>;
119 };
120 };