tjh.dev
Linux kernel mirror (for testing)
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linux
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller
8
9maintainers:
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
12
13properties:
14 compatible:
15 oneOf:
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
25 - mediatek,mt8135-mmc
26 - mediatek,mt8173-mmc
27 - mediatek,mt8183-mmc
28 - mediatek,mt8196-mmc
29 - mediatek,mt8516-mmc
30 - items:
31 - const: mediatek,mt7623-mmc
32 - const: mediatek,mt2701-mmc
33 - items:
34 - enum:
35 - mediatek,mt8186-mmc
36 - mediatek,mt8188-mmc
37 - mediatek,mt8192-mmc
38 - mediatek,mt8195-mmc
39 - mediatek,mt8365-mmc
40 - const: mediatek,mt8183-mmc
41
42 reg:
43 minItems: 1
44 items:
45 - description: base register (required).
46 - description: top base register (required for MT8183).
47
48 clocks:
49 description:
50 Should contain phandle for the clock feeding the MMC controller.
51 minItems: 2
52 maxItems: 7
53
54 clock-names:
55 minItems: 2
56 maxItems: 7
57
58 interrupts:
59 description:
60 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
61 interrupt is required and be configured as wakeup source irq.
62 minItems: 1
63 maxItems: 2
64
65 interrupt-names:
66 items:
67 - const: msdc
68 - const: sdio_wakeup
69
70 pinctrl-names:
71 description:
72 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
73 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
74 scenario.
75 minItems: 2
76 items:
77 - const: default
78 - const: state_uhs
79 - const: state_eint
80
81 pinctrl-0:
82 description:
83 should contain default/high speed pin ctrl.
84 maxItems: 1
85
86 pinctrl-1:
87 description:
88 should contain uhs mode pin ctrl.
89 maxItems: 1
90
91 pinctrl-2:
92 description:
93 should switch dat1 pin to GPIO mode.
94 maxItems: 1
95
96 hs400-ds-delay:
97 $ref: /schemas/types.yaml#/definitions/uint32
98 description:
99 HS400 DS delay setting.
100 minimum: 0
101 maximum: 0xffffffff
102
103 mediatek,hs200-cmd-int-delay:
104 $ref: /schemas/types.yaml#/definitions/uint32
105 description:
106 HS200 command internal delay setting.
107 This field has total 32 stages.
108 The value is an integer from 0 to 31.
109 minimum: 0
110 maximum: 31
111
112 mediatek,hs400-cmd-int-delay:
113 $ref: /schemas/types.yaml#/definitions/uint32
114 description:
115 HS400 command internal delay setting.
116 This field has total 32 stages.
117 The value is an integer from 0 to 31.
118 minimum: 0
119 maximum: 31
120
121 mediatek,hs400-cmd-resp-sel-rising:
122 $ref: /schemas/types.yaml#/definitions/flag
123 description:
124 HS400 command response sample selection.
125 If present, HS400 command responses are sampled on rising edges.
126 If not present, HS400 command responses are sampled on falling edges.
127
128 mediatek,hs400-ds-dly3:
129 $ref: /schemas/types.yaml#/definitions/uint32
130 description:
131 Gear of the third delay line for DS for input data latch in data
132 pad macro, there are 32 stages from 0 to 31.
133 For different corner IC, the time is different about one step, it is
134 about 100ps.
135 The value is confirmed by doing scan and calibration to find a best
136 value with corner IC and it is valid only for HS400 mode.
137 minimum: 0
138 maximum: 31
139
140 mediatek,latch-ck:
141 $ref: /schemas/types.yaml#/definitions/uint32
142 description:
143 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
144 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
145 if not present, default value is 0.
146 applied to compatible "mediatek,mt2701-mmc".
147 minimum: 0
148 maximum: 7
149
150 mediatek,tuning-step:
151 $ref: /schemas/types.yaml#/definitions/uint32
152 description:
153 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
154 If not present, default tuning step is 32. For eMMC and SD, this can yield
155 satisfactory calibration results in most cases.
156 enum: [32, 64]
157 default: 32
158
159 resets:
160 maxItems: 1
161
162 reset-names:
163 const: hrst
164
165required:
166 - compatible
167 - reg
168 - interrupts
169 - clocks
170 - clock-names
171 - pinctrl-names
172 - pinctrl-0
173 - pinctrl-1
174 - vmmc-supply
175 - vqmmc-supply
176
177allOf:
178 - $ref: mmc-controller.yaml#
179 - if:
180 properties:
181 compatible:
182 enum:
183 - mediatek,mt2701-mmc
184 - mediatek,mt6779-mmc
185 - mediatek,mt6795-mmc
186 - mediatek,mt7620-mmc
187 - mediatek,mt7622-mmc
188 - mediatek,mt7623-mmc
189 - mediatek,mt8135-mmc
190 - mediatek,mt8173-mmc
191 - mediatek,mt8183-mmc
192 - mediatek,mt8186-mmc
193 - mediatek,mt8188-mmc
194 - mediatek,mt8195-mmc
195 - mediatek,mt8196-mmc
196 - mediatek,mt8516-mmc
197 then:
198 properties:
199 clocks:
200 minItems: 2
201 items:
202 - description: source clock
203 - description: HCLK which used for host
204 - description: independent source clock gate
205 clock-names:
206 minItems: 2
207 items:
208 - const: source
209 - const: hclk
210 - const: source_cg
211
212 - if:
213 properties:
214 compatible:
215 contains:
216 const: mediatek,mt2712-mmc
217 then:
218 properties:
219 clocks:
220 minItems: 3
221 items:
222 - description: source clock
223 - description: HCLK which used for host
224 - description: independent source clock gate
225 - description: bus clock used for internal register access (required for MSDC0/3).
226 clock-names:
227 minItems: 3
228 items:
229 - const: source
230 - const: hclk
231 - const: source_cg
232 - const: bus_clk
233
234 - if:
235 properties:
236 compatible:
237 contains:
238 enum:
239 - mediatek,mt7986-mmc
240 - mediatek,mt7988-mmc
241 - mediatek,mt8183-mmc
242 - mediatek,mt8196-mmc
243 then:
244 properties:
245 reg:
246 minItems: 2
247 else:
248 properties:
249 reg:
250 maxItems: 1
251
252 - if:
253 properties:
254 compatible:
255 contains:
256 enum:
257 - mediatek,mt7986-mmc
258 then:
259 properties:
260 clocks:
261 minItems: 3
262 items:
263 - description: source clock
264 - description: HCLK which used for host
265 - description: independent source clock gate
266 - description: bus clock used for internal register access (required for MSDC0/3).
267 - description: msdc subsys clock gate
268 clock-names:
269 minItems: 3
270 items:
271 - const: source
272 - const: hclk
273 - const: source_cg
274 - const: bus_clk
275 - const: sys_cg
276
277 - if:
278 properties:
279 compatible:
280 contains:
281 enum:
282 - mediatek,mt7988-mmc
283 then:
284 properties:
285 clocks:
286 items:
287 - description: source clock
288 - description: HCLK which used for host
289 - description: Advanced eXtensible Interface
290 - description: Advanced High-performance Bus clock
291 clock-names:
292 items:
293 - const: source
294 - const: hclk
295 - const: axi_cg
296 - const: ahb_cg
297
298 - if:
299 properties:
300 compatible:
301 enum:
302 - mediatek,mt8186-mmc
303 - mediatek,mt8188-mmc
304 - mediatek,mt8195-mmc
305 then:
306 properties:
307 clocks:
308 items:
309 - description: source clock
310 - description: HCLK which used for host
311 - description: independent source clock gate
312 - description: crypto clock used for data encrypt/decrypt (optional)
313 clock-names:
314 items:
315 - const: source
316 - const: hclk
317 - const: source_cg
318 - const: crypto
319
320 - if:
321 properties:
322 compatible:
323 contains:
324 const: mediatek,mt8192-mmc
325 then:
326 properties:
327 clocks:
328 items:
329 - description: source clock
330 - description: HCLK which used for host
331 - description: independent source clock gate
332 - description: msdc subsys clock gate
333 - description: peripheral bus clock gate
334 - description: AXI bus clock gate
335 - description: AHB bus clock gate
336 clock-names:
337 items:
338 - const: source
339 - const: hclk
340 - const: source_cg
341 - const: sys_cg
342 - const: pclk_cg
343 - const: axi_cg
344 - const: ahb_cg
345
346unevaluatedProperties: false
347
348examples:
349 - |
350 #include <dt-bindings/interrupt-controller/irq.h>
351 #include <dt-bindings/interrupt-controller/arm-gic.h>
352 #include <dt-bindings/clock/mt8173-clk.h>
353 mmc0: mmc@11230000 {
354 compatible = "mediatek,mt8173-mmc";
355 reg = <0x11230000 0x1000>;
356 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
357 vmmc-supply = <&mt6397_vemc_3v3_reg>;
358 vqmmc-supply = <&mt6397_vio18_reg>;
359 clocks = <&pericfg CLK_PERI_MSDC30_0>,
360 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
361 clock-names = "source", "hclk";
362 pinctrl-names = "default", "state_uhs";
363 pinctrl-0 = <&mmc0_pins_default>;
364 pinctrl-1 = <&mmc0_pins_uhs>;
365 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
366 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
367 hs400-ds-delay = <0x14015>;
368 mediatek,hs200-cmd-int-delay = <26>;
369 mediatek,hs400-cmd-int-delay = <14>;
370 mediatek,hs400-cmd-resp-sel-rising;
371 };
372
373 mmc3: mmc@11260000 {
374 compatible = "mediatek,mt8173-mmc";
375 reg = <0x11260000 0x1000>;
376 clock-names = "source", "hclk";
377 clocks = <&pericfg CLK_PERI_MSDC30_3>,
378 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
379 interrupt-names = "msdc", "sdio_wakeup";
380 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
381 <&pio 23 IRQ_TYPE_LEVEL_LOW>;
382 pinctrl-names = "default", "state_uhs", "state_eint";
383 pinctrl-0 = <&mmc2_pins_default>;
384 pinctrl-1 = <&mmc2_pins_uhs>;
385 pinctrl-2 = <&mmc2_pins_eint>;
386 bus-width = <4>;
387 max-frequency = <200000000>;
388 cap-sd-highspeed;
389 sd-uhs-sdr104;
390 keep-power-in-suspend;
391 wakeup-source;
392 cap-sdio-irq;
393 no-mmc;
394 no-sd;
395 non-removable;
396 vmmc-supply = <&sdio_fixed_3v3>;
397 vqmmc-supply = <&mt6397_vgp3_reg>;
398 mmc-pwrseq = <&wifi_pwrseq>;
399 };
400
401...