tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MIPS Coherence Manager
8
9description:
10 The Coherence Manager (CM) is responsible for establishing the
11 global ordering of requests from all elements of the system and
12 sending the correct data back to the requester. It supports Cache
13 to Cache transfers.
14 https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf
15 https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf
16
17maintainers:
18 - Jiaxun Yang <jiaxun.yang@flygoat.com>
19
20properties:
21 compatible:
22 oneOf:
23 - const: mti,mips-cm
24 - const: mobileye,eyeq6-cm
25 description:
26 On EyeQ6 the HCI (Hardware Cache Initialization) information for
27 the L2 cache in multi-cluster configuration is broken.
28
29 reg:
30 description:
31 Base address and size of the Global Configuration Registers
32 referred to as CMGCR.They are the system programmer's interface
33 to the Coherency Manager. Their location in the memory map is
34 determined at core build time. In a functional system, the base
35 address is provided by the Coprocessor 0, but some
36 System-on-Chip (SoC) designs may not provide an accurate address
37 that needs to be described statically.
38
39 maxItems: 1
40
41required:
42 - compatible
43
44additionalProperties: false
45
46examples:
47 - |
48 coherency-manager@1fbf8000 {
49 compatible = "mti,mips-cm";
50 reg = <0x1bde8000 0x8000>;
51 };
52
53 - |
54 coherency-manager {
55 compatible = "mobileye,eyeq6-cm";
56 };
57...