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Linux kernel mirror (for testing)
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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#ifndef __MSM_DRM_H__
26#define __MSM_DRM_H__
27
28#include "drm.h"
29
30#if defined(__cplusplus)
31extern "C" {
32#endif
33
34/* Please note that modifications to all structs defined here are
35 * subject to backwards-compatibility constraints:
36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
37 * user/kernel compatibility
38 * 2) Keep fields aligned to their size
39 * 3) Because of how drm_ioctl() works, we can add new fields at
40 * the end of an ioctl if some care is taken: drm_ioctl() will
41 * zero out the new fields at the tail of the ioctl, so a zero
42 * value should have a backwards compatible meaning. And for
43 * output params, userspace won't see the newly added output
44 * fields.. so that has to be somehow ok.
45 */
46
47#define MSM_PIPE_NONE 0x00
48#define MSM_PIPE_2D0 0x01
49#define MSM_PIPE_2D1 0x02
50#define MSM_PIPE_3D0 0x10
51
52/* The pipe-id just uses the lower bits, so can be OR'd with flags in
53 * the upper 16 bits (which could be extended further, if needed, maybe
54 * we extend/overload the pipe-id some day to deal with multiple rings,
55 * but even then I don't think we need the full lower 16 bits).
56 */
57#define MSM_PIPE_ID_MASK 0xffff
58#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
59#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
60
61/* timeouts are specified in clock-monotonic absolute times (to simplify
62 * restarting interrupted ioctls). The following struct is logically the
63 * same as 'struct timespec' but 32/64b ABI safe.
64 */
65struct drm_msm_timespec {
66 __s64 tv_sec; /* seconds */
67 __s64 tv_nsec; /* nanoseconds */
68};
69
70/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
71 * "RW" indicates a param that can be both read (GET_PARAM) and written
72 * (SET_PARAM)
73 */
74#define MSM_PARAM_GPU_ID 0x01 /* RO */
75#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
76#define MSM_PARAM_CHIP_ID 0x03 /* RO */
77#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
78#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
79#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
80#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
81#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
82#define MSM_PARAM_FAULTS 0x09 /* RO */
83#define MSM_PARAM_SUSPENDS 0x0a /* RO */
84#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
85#define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
86#define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */
87#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
88#define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */
89#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
90#define MSM_PARAM_RAYTRACING 0x11 /* RO */
91#define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */
92#define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */
93#define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */
94
95/* For backwards compat. The original support for preemption was based on
96 * a single ring per priority level so # of priority levels equals the #
97 * of rings. With drm/scheduler providing additional levels of priority,
98 * the number of priorities is greater than the # of rings. The param is
99 * renamed to better reflect this.
100 */
101#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
102
103struct drm_msm_param {
104 __u32 pipe; /* in, MSM_PIPE_x */
105 __u32 param; /* in, MSM_PARAM_x */
106 __u64 value; /* out (get_param) or in (set_param) */
107 __u32 len; /* zero for non-pointer params */
108 __u32 pad; /* must be zero */
109};
110
111/*
112 * GEM buffers:
113 */
114
115#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
116#define MSM_BO_GPU_READONLY 0x00000002
117#define MSM_BO_CACHE_MASK 0x000f0000
118/* cache modes */
119#define MSM_BO_CACHED 0x00010000
120#define MSM_BO_WC 0x00020000
121#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
122#define MSM_BO_CACHED_COHERENT 0x080000
123
124#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
125 MSM_BO_GPU_READONLY | \
126 MSM_BO_CACHE_MASK)
127
128struct drm_msm_gem_new {
129 __u64 size; /* in */
130 __u32 flags; /* in, mask of MSM_BO_x */
131 __u32 handle; /* out */
132};
133
134/* Get or set GEM buffer info. The requested value can be passed
135 * directly in 'value', or for data larger than 64b 'value' is a
136 * pointer to userspace buffer, with 'len' specifying the number of
137 * bytes copied into that buffer. For info returned by pointer,
138 * calling the GEM_INFO ioctl with null 'value' will return the
139 * required buffer size in 'len'
140 */
141#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
142#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
143#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
144#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
145#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
146#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
147#define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */
148#define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */
149
150struct drm_msm_gem_info {
151 __u32 handle; /* in */
152 __u32 info; /* in - one of MSM_INFO_* */
153 __u64 value; /* in or out */
154 __u32 len; /* in or out */
155 __u32 pad;
156};
157
158#define MSM_PREP_READ 0x01
159#define MSM_PREP_WRITE 0x02
160#define MSM_PREP_NOSYNC 0x04
161#define MSM_PREP_BOOST 0x08
162
163#define MSM_PREP_FLAGS (MSM_PREP_READ | \
164 MSM_PREP_WRITE | \
165 MSM_PREP_NOSYNC | \
166 MSM_PREP_BOOST | \
167 0)
168
169struct drm_msm_gem_cpu_prep {
170 __u32 handle; /* in */
171 __u32 op; /* in, mask of MSM_PREP_x */
172 struct drm_msm_timespec timeout; /* in */
173};
174
175struct drm_msm_gem_cpu_fini {
176 __u32 handle; /* in */
177};
178
179/*
180 * Cmdstream Submission:
181 */
182
183/* The value written into the cmdstream is logically:
184 *
185 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
186 *
187 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
188 * with this by emit'ing two reloc entries with appropriate shift
189 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
190 *
191 * NOTE that reloc's must be sorted by order of increasing submit_offset,
192 * otherwise EINVAL.
193 */
194struct drm_msm_gem_submit_reloc {
195 __u32 submit_offset; /* in, offset from submit_bo */
196#ifdef __cplusplus
197 __u32 _or; /* in, value OR'd with result */
198#else
199 __u32 or; /* in, value OR'd with result */
200#endif
201 __s32 shift; /* in, amount of left shift (can be negative) */
202 __u32 reloc_idx; /* in, index of reloc_bo buffer */
203 __u64 reloc_offset; /* in, offset from start of reloc_bo */
204};
205
206/* submit-types:
207 * BUF - this cmd buffer is executed normally.
208 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
209 * processed normally, but the kernel does not setup an IB to
210 * this buffer in the first-level ringbuffer
211 * CTX_RESTORE_BUF - only executed if there has been a GPU context
212 * switch since the last SUBMIT ioctl
213 */
214#define MSM_SUBMIT_CMD_BUF 0x0001
215#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
216#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
217struct drm_msm_gem_submit_cmd {
218 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
219 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
220 __u32 submit_offset; /* in, offset into submit_bo */
221 __u32 size; /* in, cmdstream size */
222 __u32 pad;
223 __u32 nr_relocs; /* in, number of submit_reloc's */
224 __u64 relocs; /* in, ptr to array of submit_reloc's */
225};
226
227/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
228 * cmdstream buffer(s) themselves or reloc entries) has one (and only
229 * one) entry in the submit->bos[] table.
230 *
231 * As a optimization, the current buffer (gpu virtual address) can be
232 * passed back through the 'presumed' field. If on a subsequent reloc,
233 * userspace passes back a 'presumed' address that is still valid,
234 * then patching the cmdstream for this entry is skipped. This can
235 * avoid kernel needing to map/access the cmdstream bo in the common
236 * case.
237 */
238#define MSM_SUBMIT_BO_READ 0x0001
239#define MSM_SUBMIT_BO_WRITE 0x0002
240#define MSM_SUBMIT_BO_DUMP 0x0004
241#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
242
243#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
244 MSM_SUBMIT_BO_WRITE | \
245 MSM_SUBMIT_BO_DUMP | \
246 MSM_SUBMIT_BO_NO_IMPLICIT)
247
248struct drm_msm_gem_submit_bo {
249 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
250 __u32 handle; /* in, GEM handle */
251 __u64 presumed; /* in/out, presumed buffer address */
252};
253
254/* Valid submit ioctl flags: */
255#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
256#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
257#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
258#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
259#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
260#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
261#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
262#define MSM_SUBMIT_FLAGS ( \
263 MSM_SUBMIT_NO_IMPLICIT | \
264 MSM_SUBMIT_FENCE_FD_IN | \
265 MSM_SUBMIT_FENCE_FD_OUT | \
266 MSM_SUBMIT_SUDO | \
267 MSM_SUBMIT_SYNCOBJ_IN | \
268 MSM_SUBMIT_SYNCOBJ_OUT | \
269 MSM_SUBMIT_FENCE_SN_IN | \
270 0)
271
272#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
273#define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
274 MSM_SUBMIT_SYNCOBJ_RESET | \
275 0)
276
277struct drm_msm_gem_submit_syncobj {
278 __u32 handle; /* in, syncobj handle. */
279 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
280 __u64 point; /* in, timepoint for timeline syncobjs. */
281};
282
283/* Each cmdstream submit consists of a table of buffers involved, and
284 * one or more cmdstream buffers. This allows for conditional execution
285 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
286 */
287struct drm_msm_gem_submit {
288 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
289 __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
290 __u32 nr_bos; /* in, number of submit_bo's */
291 __u32 nr_cmds; /* in, number of submit_cmd's */
292 __u64 bos; /* in, ptr to array of submit_bo's */
293 __u64 cmds; /* in, ptr to array of submit_cmd's */
294 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
295 __u32 queueid; /* in, submitqueue id */
296 __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
297 __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
298 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
299 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
300 __u32 syncobj_stride; /* in, stride of syncobj arrays. */
301 __u32 pad; /*in, reserved for future use, always 0. */
302
303};
304
305#define MSM_WAIT_FENCE_BOOST 0x00000001
306#define MSM_WAIT_FENCE_FLAGS ( \
307 MSM_WAIT_FENCE_BOOST | \
308 0)
309
310/* The normal way to synchronize with the GPU is just to CPU_PREP on
311 * a buffer if you need to access it from the CPU (other cmdstream
312 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
313 * handle the required synchronization under the hood). This ioctl
314 * mainly just exists as a way to implement the gallium pipe_fence
315 * APIs without requiring a dummy bo to synchronize on.
316 */
317struct drm_msm_wait_fence {
318 __u32 fence; /* in */
319 __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */
320 struct drm_msm_timespec timeout; /* in */
321 __u32 queueid; /* in, submitqueue id */
322};
323
324/* madvise provides a way to tell the kernel in case a buffers contents
325 * can be discarded under memory pressure, which is useful for userspace
326 * bo cache where we want to optimistically hold on to buffer allocate
327 * and potential mmap, but allow the pages to be discarded under memory
328 * pressure.
329 *
330 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
331 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
332 * In the WILLNEED case, 'retained' indicates to userspace whether the
333 * backing pages still exist.
334 */
335#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
336#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
337#define __MSM_MADV_PURGED 2 /* internal state */
338
339struct drm_msm_gem_madvise {
340 __u32 handle; /* in, GEM handle */
341 __u32 madv; /* in, MSM_MADV_x */
342 __u32 retained; /* out, whether backing store still exists */
343};
344
345/*
346 * Draw queues allow the user to set specific submission parameter. Command
347 * submissions specify a specific submitqueue to use. ID 0 is reserved for
348 * backwards compatibility as a "default" submitqueue
349 */
350
351#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001
352#define MSM_SUBMITQUEUE_FLAGS ( \
353 MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
354 0)
355
356/*
357 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
358 * a lower numeric value is higher priority.
359 */
360struct drm_msm_submitqueue {
361 __u32 flags; /* in, MSM_SUBMITQUEUE_x */
362 __u32 prio; /* in, Priority level */
363 __u32 id; /* out, identifier */
364};
365
366#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
367
368struct drm_msm_submitqueue_query {
369 __u64 data;
370 __u32 id;
371 __u32 param;
372 __u32 len;
373 __u32 pad;
374};
375
376#define DRM_MSM_GET_PARAM 0x00
377#define DRM_MSM_SET_PARAM 0x01
378#define DRM_MSM_GEM_NEW 0x02
379#define DRM_MSM_GEM_INFO 0x03
380#define DRM_MSM_GEM_CPU_PREP 0x04
381#define DRM_MSM_GEM_CPU_FINI 0x05
382#define DRM_MSM_GEM_SUBMIT 0x06
383#define DRM_MSM_WAIT_FENCE 0x07
384#define DRM_MSM_GEM_MADVISE 0x08
385/* placeholder:
386#define DRM_MSM_GEM_SVM_NEW 0x09
387 */
388#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
389#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
390#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
391
392#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
393#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
394#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
395#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
396#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
397#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
398#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
399#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
400#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
401#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
402#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
403#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
404
405#if defined(__cplusplus)
406}
407#endif
408
409#endif /* __MSM_DRM_H__ */