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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTMIPS SoCs System Controller
8
9maintainers:
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12description: |
13 MediaTek MIPS and Ralink SoCs provides a system controller to allow
14 to access to system control registers. These registers include clock
15 and reset related ones so this node is both clock and reset provider
16 for the rest of the world.
17
18 These SoCs have an XTAL from where the cpu clock is
19 provided as well as derived clocks for the bus and the peripherals.
20
21 Each clock is assigned an identifier and client nodes use this identifier
22 to specify the clock which they consume.
23
24 All these identifiers could be found in:
25 [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
26
27properties:
28 compatible:
29 items:
30 - enum:
31 - ralink,mt7620-sysc
32 - ralink,mt7628-sysc
33 - ralink,mt7688-sysc
34 - ralink,rt2880-sysc
35 - ralink,rt3050-sysc
36 - ralink,rt3052-sysc
37 - ralink,rt3352-sysc
38 - ralink,rt3883-sysc
39 - ralink,rt5350-sysc
40 - const: syscon
41
42 reg:
43 maxItems: 1
44
45 '#clock-cells':
46 description:
47 The first cell indicates the clock number, see [1] for available
48 clocks.
49 const: 1
50
51 '#reset-cells':
52 description:
53 The first cell indicates the reset bit within the register.
54 const: 1
55
56required:
57 - compatible
58 - reg
59 - '#clock-cells'
60 - '#reset-cells'
61
62additionalProperties: false
63
64examples:
65 - |
66 #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
67
68 syscon@0 {
69 compatible = "ralink,rt5350-sysc", "syscon";
70 reg = <0x0 0x100>;
71 #clock-cells = <1>;
72 #reset-cells = <1>;
73 };