tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
12
13description:
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24 their implementation lacks a memory-mapped MTIME register, thus not
25 compatible with SiFive ones.
26
27properties:
28 compatible:
29 oneOf:
30 - items:
31 - enum:
32 - canaan,k210-clint # Canaan Kendryte K210
33 - sifive,fu540-c000-clint # SiFive FU540
34 - spacemit,k1-clint # SpacemiT K1
35 - starfive,jh7100-clint # StarFive JH7100
36 - starfive,jh7110-clint # StarFive JH7110
37 - starfive,jh8100-clint # StarFive JH8100
38 - const: sifive,clint0 # SiFive CLINT v0 IP block
39 - items:
40 - {}
41 - const: sifive,clint2 # SiFive CLINT v2 IP block
42 description:
43 SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
44 differs from that of sifive,clint0, making them incompatible.
45 - items:
46 - enum:
47 - allwinner,sun20i-d1-clint
48 - sophgo,cv1800b-clint
49 - sophgo,cv1812h-clint
50 - sophgo,sg2002-clint
51 - thead,th1520-clint
52 - const: thead,c900-clint
53 - items:
54 - const: sifive,clint0
55 - const: riscv,clint0
56 deprecated: true
57 description: For the QEMU virt machine only
58
59 description:
60 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
61 when compatible with a SiFive CLINT. Please refer to
62 sifive-blocks-ip-versioning.txt for details regarding the latter.
63
64 reg:
65 maxItems: 1
66
67 interrupts-extended:
68 minItems: 1
69 maxItems: 4095
70
71 sifive,fine-ctr-bits:
72 maximum: 15
73 description: The width in bits of the fine counter.
74
75if:
76 properties:
77 compatible:
78 contains:
79 const: sifive,clint2
80then:
81 required:
82 - sifive,fine-ctr-bits
83else:
84 properties:
85 sifive,fine-ctr-bits: false
86
87additionalProperties: false
88
89required:
90 - compatible
91 - reg
92 - interrupts-extended
93
94examples:
95 - |
96 timer@2000000 {
97 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
98 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
99 <&cpu2intc 3>, <&cpu2intc 7>,
100 <&cpu3intc 3>, <&cpu3intc 7>,
101 <&cpu4intc 3>, <&cpu4intc 7>;
102 reg = <0x2000000 0x10000>;
103 };
104...