tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx clocking wizard
8
9maintainers:
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11
12description:
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
14 reads required input clock frequencies from the devicetree and acts as clock
15 clock output.
16
17properties:
18 compatible:
19 enum:
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard
24
25
26 reg:
27 maxItems: 1
28
29 "#clock-cells":
30 const: 1
31
32 clocks:
33 items:
34 - description: clock input
35 - description: axi clock
36
37 clock-names:
38 items:
39 - const: clk_in1
40 - const: s_axi_aclk
41
42 xlnx,static-config:
43 $ref: /schemas/types.yaml#/definitions/flag
44 description:
45 Indicate whether the core has been configured without support for dynamic
46 runtime reconfguration of the clocking primitive MMCM/PLL.
47
48 xlnx,speed-grade:
49 $ref: /schemas/types.yaml#/definitions/uint32
50 enum: [1, 2, 3]
51 description:
52 Speed grade of the device. Higher the speed grade faster is the FPGA device.
53
54 xlnx,nr-outputs:
55 $ref: /schemas/types.yaml#/definitions/uint32
56 minimum: 1
57 maximum: 8
58 description:
59 Number of outputs.
60
61required:
62 - compatible
63 - reg
64 - "#clock-cells"
65 - clocks
66 - clock-names
67 - xlnx,speed-grade
68 - xlnx,nr-outputs
69
70additionalProperties: false
71
72examples:
73 - |
74 clock-controller@b0000000 {
75 compatible = "xlnx,clocking-wizard";
76 reg = <0xb0000000 0x10000>;
77 #clock-cells = <1>;
78 xlnx,static-config;
79 xlnx,speed-grade = <1>;
80 xlnx,nr-outputs = <6>;
81 clock-names = "clk_in1", "s_axi_aclk";
82 clocks = <&clkc 15>, <&clkc 15>;
83 };
84...