tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
9
10maintainers:
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
13
14description:
15 This file documents platform glue layer for stmmac.
16
17# We need a select here so we don't match all nodes with 'snps,dwmac'
18select:
19 properties:
20 compatible:
21 contains:
22 enum:
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
27 required:
28 - compatible
29
30properties:
31 compatible:
32 oneOf:
33 - items:
34 - enum:
35 - st,stm32mp25-dwmac
36 - const: snps,dwmac-5.20
37 - items:
38 - enum:
39 - st,stm32mp1-dwmac
40 - st,stm32mp13-dwmac
41 - const: snps,dwmac-4.20a
42 - items:
43 - enum:
44 - st,stm32-dwmac
45 - const: snps,dwmac-4.10a
46 - items:
47 - enum:
48 - st,stm32-dwmac
49 - const: snps,dwmac-3.50a
50
51 reg: true
52
53 reg-names:
54 items:
55 - const: stmmaceth
56
57 interrupts:
58 minItems: 1
59 maxItems: 2
60
61 interrupt-names:
62 minItems: 1
63 items:
64 - const: macirq
65 - const: eth_wake_irq
66
67 clocks:
68 minItems: 3
69 items:
70 - description: GMAC main clock
71 - description: MAC TX clock
72 - description: MAC RX clock
73 - description: For MPU family, used for power mode
74 - description: For MPU family, used for PHY without quartz
75 - description: PTP clock
76
77 clock-names:
78 minItems: 3
79 maxItems: 6
80 contains:
81 enum:
82 - stmmaceth
83 - mac-clk-tx
84 - mac-clk-rx
85 - ethstp
86 - eth-ck
87 - ptp_ref
88
89 st,syscon:
90 $ref: /schemas/types.yaml#/definitions/phandle-array
91 items:
92 - minItems: 2
93 items:
94 - description: phandle to the syscon node which encompases the glue register
95 - description: offset of the control register
96 - description: field to set mask in register
97 description:
98 Should be phandle/offset pair. The phandle to the syscon node which
99 encompases the glue register, the offset of the control register and
100 the mask to set bitfield in control register
101
102 st,ext-phyclk:
103 description:
104 set this property in RMII mode when you have PHY without crystal 50MHz and want to
105 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
106 RCC clock instead of ETH_CLK125.
107 type: boolean
108
109 st,eth-clk-sel:
110 description:
111 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
112 type: boolean
113
114 st,eth-ref-clk-sel:
115 description:
116 set this property in RMII mode when you have PHY without crystal 50MHz and want to
117 select RCC clock instead of ETH_REF_CLK.
118 type: boolean
119
120 access-controllers:
121 minItems: 1
122 maxItems: 2
123
124required:
125 - compatible
126 - clocks
127 - clock-names
128 - st,syscon
129
130unevaluatedProperties: false
131
132allOf:
133 - $ref: snps,dwmac.yaml#
134 - if:
135 properties:
136 compatible:
137 contains:
138 enum:
139 - st,stm32-dwmac
140 - st,stm32mp1-dwmac
141 - st,stm32mp25-dwmac
142 then:
143 properties:
144 st,syscon:
145 items:
146 minItems: 2
147 maxItems: 2
148
149 - if:
150 properties:
151 compatible:
152 contains:
153 enum:
154 - st,stm32mp13-dwmac
155 then:
156 properties:
157 st,syscon:
158 items:
159 minItems: 3
160 maxItems: 3
161
162examples:
163 - |
164 #include <dt-bindings/interrupt-controller/arm-gic.h>
165 #include <dt-bindings/clock/stm32mp1-clks.h>
166 //Example 1
167 ethernet0: ethernet@5800a000 {
168 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
169 reg = <0x5800a000 0x2000>;
170 reg-names = "stmmaceth";
171 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
172 interrupt-names = "macirq";
173 clock-names = "stmmaceth",
174 "mac-clk-tx",
175 "mac-clk-rx",
176 "ethstp",
177 "eth-ck";
178 clocks = <&rcc ETHMAC>,
179 <&rcc ETHTX>,
180 <&rcc ETHRX>,
181 <&rcc ETHSTP>,
182 <&rcc ETHCK_K>;
183 st,syscon = <&syscfg 0x4>;
184 snps,pbl = <2>;
185 snps,axi-config = <&stmmac_axi_config_0>;
186 snps,tso;
187 phy-mode = "rgmii";
188 };
189
190 - |
191 //Example 2 (MCU example)
192 ethernet1: ethernet@40028000 {
193 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
194 reg = <0x40028000 0x8000>;
195 reg-names = "stmmaceth";
196 interrupts = <0 61 0>, <0 62 0>;
197 interrupt-names = "macirq", "eth_wake_irq";
198 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
199 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
200 st,syscon = <&syscfg 0x4>;
201 snps,pbl = <8>;
202 snps,mixed-burst;
203 phy-mode = "mii";
204 };
205
206 - |
207 //Example 3
208 ethernet2: ethernet@40027000 {
209 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
210 reg = <0x40028000 0x8000>;
211 reg-names = "stmmaceth";
212 interrupts = <61>;
213 interrupt-names = "macirq";
214 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
215 clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
216 st,syscon = <&syscfg 0x4>;
217 snps,pbl = <8>;
218 phy-mode = "mii";
219 };