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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef _XE_MI_COMMANDS_H_
7#define _XE_MI_COMMANDS_H_
8
9#include "instructions/xe_instr_defs.h"
10
11/*
12 * MI (Memory Interface) commands are supported by all GT engines. They
13 * provide general memory operations and command streamer control. MI commands
14 * have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction
15 * header dword and a specific MI opcode in bits 28:23.
16 */
17
18#define MI_OPCODE REG_GENMASK(28, 23)
19#define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */
20
21#define __MI_INSTR(opcode) \
22 (XE_INSTR_MI | REG_FIELD_PREP(MI_OPCODE, opcode))
23
24#define MI_NOOP __MI_INSTR(0x0)
25#define MI_USER_INTERRUPT __MI_INSTR(0x2)
26#define MI_ARB_CHECK __MI_INSTR(0x5)
27
28#define MI_ARB_ON_OFF __MI_INSTR(0x8)
29#define MI_ARB_ENABLE REG_BIT(0)
30#define MI_ARB_DISABLE 0x0
31
32#define MI_BATCH_BUFFER_END __MI_INSTR(0xA)
33#define MI_TOPOLOGY_FILTER __MI_INSTR(0xD)
34#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
35
36#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
37#define MI_SDI_GGTT REG_BIT(22)
38#define MI_SDI_LEN_DW GENMASK(9, 0)
39#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
40#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
41 REG_BIT(21))
42
43#define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22)
44#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
45#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
46#define MI_LRI_NUM_REGS(x) XE_INSTR_NUM_DW(2 * (x) + 1)
47#define MI_LRI_FORCE_POSTED REG_BIT(12)
48#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
49
50#define MI_FLUSH_DW __MI_INSTR(0x26)
51#define MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22)
52#define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
53#define MI_INVALIDATE_TLB REG_BIT(18)
54#define MI_FLUSH_DW_CCS REG_BIT(16)
55#define MI_FLUSH_DW_OP_STOREDW REG_BIT(14)
56#define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0)
57#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2)
58#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)
59#define MI_FLUSH_DW_USE_GTT REG_BIT(2)
60
61#define MI_LOAD_REGISTER_MEM (__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
62#define MI_LRM_USE_GGTT REG_BIT(22)
63
64#define MI_COPY_MEM_MEM (__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))
65#define MI_COPY_MEM_MEM_SRC_GGTT REG_BIT(22)
66#define MI_COPY_MEM_MEM_DST_GGTT REG_BIT(21)
67
68#define MI_BATCH_BUFFER_START __MI_INSTR(0x31)
69
70#define MI_SET_APPID __MI_INSTR(0x0e)
71#define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0)
72#define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
73
74#endif