tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
4#define __SOC_MEDIATEK_MT8186_MMSYS_H
5
6/* Values for DPI configuration in MMSYS address space */
7#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
8#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
9#define MT8186_DPI_RGB888_SDR_CON 0
10#define MT8186_DPI_RGB888_DDR_CON 1
11#define MT8186_DPI_RGB565_SDR_CON 2
12#define MT8186_DPI_RGB565_DDR_CON 3
13
14#define MT8186_MMSYS_OVL_CON 0xF04
15#define MT8186_MMSYS_OVL0_CON_MASK 0x3
16#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
17#define MT8186_OVL0_GO_BLEND BIT(0)
18#define MT8186_OVL0_GO_BG BIT(1)
19#define MT8186_OVL0_2L_GO_BLEND BIT(2)
20#define MT8186_OVL0_2L_GO_BG BIT(3)
21#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
22#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
23#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
24#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
25#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
26#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
27#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
28#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
29#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
30#define MT8186_DISP_OVL0_MOUT_EN 0xF18
31#define MT8186_OVL0_MOUT_EN_MASK 0xF
32#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
33#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
34#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
35#define MT8186_DITHER0_MOUT_EN_MASK 0xF
36#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
37#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
38#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
39#define MT8186_DISP_RDMA0_SEL_IN 0xF28
40#define MT8186_RDMA0_SEL_IN_MASK 0xF
41#define MT8186_RDMA0_FROM_OVL0 0
42#define MT8186_RDMA0_FROM_OVL0_2L 2
43#define MT8186_DISP_DSI0_SEL_IN 0xF30
44#define MT8186_DSI0_SEL_IN_MASK 0xF
45#define MT8186_DSI0_FROM_RDMA0 0
46#define MT8186_DSI0_FROM_DITHER0 1
47#define MT8186_DSI0_FROM_RDMA1 2
48#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
49#define MT8186_RDMA1_MOUT_EN_MASK 0xF
50#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
51#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
52#define MT8186_DISP_RDMA1_SEL_IN 0xF40
53#define MT8186_RDMA1_SEL_IN_MASK 0xF
54#define MT8186_RDMA1_FROM_OVL0 0
55#define MT8186_RDMA1_FROM_OVL0_2L 2
56#define MT8186_RDMA1_FROM_DITHER0 3
57#define MT8186_DISP_DPI0_SEL_IN 0xF44
58#define MT8186_DPI0_SEL_IN_MASK 0xF
59#define MT8186_DPI0_FROM_RDMA1 0
60#define MT8186_DPI0_FROM_DITHER0 1
61#define MT8186_DPI0_FROM_RDMA0 2
62
63#define MT8186_MMSYS_SW0_RST_B 0x160
64
65static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
66 MMSYS_ROUTE(OVL0, RDMA0,
67 MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
68 MT8186_OVL0_MOUT_TO_RDMA0),
69 MMSYS_ROUTE(OVL0, RDMA0,
70 MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
71 MT8186_RDMA0_FROM_OVL0),
72 MMSYS_ROUTE(OVL0, RDMA0,
73 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
74 MT8186_OVL0_GO_BLEND),
75 MMSYS_ROUTE(RDMA0, COLOR0,
76 MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
77 MT8186_RDMA0_SOUT_TO_COLOR0),
78 MMSYS_ROUTE(DITHER0, DSI0,
79 MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
80 MT8186_DITHER0_MOUT_TO_DSI0),
81 MMSYS_ROUTE(DITHER0, DSI0,
82 MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
83 MT8186_DSI0_FROM_DITHER0),
84 MMSYS_ROUTE(OVL_2L0, RDMA1,
85 MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
86 MT8186_OVL0_2L_MOUT_TO_RDMA1),
87 MMSYS_ROUTE(OVL_2L0, RDMA1,
88 MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
89 MT8186_RDMA1_FROM_OVL0_2L),
90 MMSYS_ROUTE(OVL_2L0, RDMA1,
91 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
92 MT8186_OVL0_2L_GO_BLEND),
93 MMSYS_ROUTE(RDMA1, DPI0,
94 MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
95 MT8186_RDMA1_MOUT_TO_DPI0_SEL),
96 MMSYS_ROUTE(RDMA1, DPI0,
97 MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
98 MT8186_DPI0_FROM_RDMA1),
99};
100
101#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */