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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <linux/completion.h>
15#include <linux/soundwire/sdw.h>
16#include <linux/soundwire/sdw_intel.h>
17#include <sound/compress_driver.h>
18#include <sound/hda_codec.h>
19#include <sound/hdaudio_ext.h>
20#include "../sof-client-probes.h"
21#include "../sof-audio.h"
22#include "shim.h"
23
24/* PCI registers */
25#define PCI_TCSEL 0x44
26#define PCI_PGCTL PCI_TCSEL
27#define PCI_CGCTL 0x48
28
29/* PCI_PGCTL bits */
30#define PCI_PGCTL_ADSPPGD BIT(2)
31#define PCI_PGCTL_LSRMD_MASK BIT(4)
32
33/* PCI_CGCTL bits */
34#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
35#define PCI_CGCTL_ADSPDCGE BIT(1)
36
37/* Legacy HDA registers and bits used - widths are variable */
38#define SOF_HDA_GCAP 0x0
39#define SOF_HDA_GCTL 0x8
40/* accept unsol. response enable */
41#define SOF_HDA_GCTL_UNSOL BIT(8)
42#define SOF_HDA_LLCH 0x14
43#define SOF_HDA_INTCTL 0x20
44#define SOF_HDA_INTSTS 0x24
45#define SOF_HDA_WAKESTS 0x0E
46#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
47#define SOF_HDA_RIRBSTS 0x5d
48
49/* SOF_HDA_GCTL register bist */
50#define SOF_HDA_GCTL_RESET BIT(0)
51
52/* SOF_HDA_INCTL regs */
53#define SOF_HDA_INT_GLOBAL_EN BIT(31)
54#define SOF_HDA_INT_CTRL_EN BIT(30)
55#define SOF_HDA_INT_ALL_STREAM 0xff
56
57/* SOF_HDA_INTSTS regs */
58#define SOF_HDA_INTSTS_GIS BIT(31)
59
60#define SOF_HDA_MAX_CAPS 10
61#define SOF_HDA_CAP_ID_OFF 16
62#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
63 SOF_HDA_CAP_ID_OFF)
64#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
65
66#define SOF_HDA_GTS_CAP_ID 0x1
67#define SOF_HDA_ML_CAP_ID 0x2
68
69#define SOF_HDA_PP_CAP_ID 0x3
70#define SOF_HDA_REG_PP_PPCH 0x10
71#define SOF_HDA_REG_PP_PPCTL 0x04
72#define SOF_HDA_REG_PP_PPSTS 0x08
73#define SOF_HDA_PPCTL_PIE BIT(31)
74#define SOF_HDA_PPCTL_GPROCEN BIT(30)
75
76/*Vendor Specific Registers*/
77#define SOF_HDA_VS_D0I3C 0x104A
78
79/* D0I3C Register fields */
80#define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
81#define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
82
83/* DPIB entry size: 8 Bytes = 2 DWords */
84#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
85
86#define SOF_HDA_SPIB_CAP_ID 0x4
87#define SOF_HDA_DRSM_CAP_ID 0x5
88
89#define SOF_HDA_SPIB_BASE 0x08
90#define SOF_HDA_SPIB_INTERVAL 0x08
91#define SOF_HDA_SPIB_SPIB 0x00
92#define SOF_HDA_SPIB_MAXFIFO 0x04
93
94#define SOF_HDA_PPHC_BASE 0x10
95#define SOF_HDA_PPHC_INTERVAL 0x10
96
97#define SOF_HDA_PPLC_BASE 0x10
98#define SOF_HDA_PPLC_MULTI 0x10
99#define SOF_HDA_PPLC_INTERVAL 0x10
100
101#define SOF_HDA_DRSM_BASE 0x08
102#define SOF_HDA_DRSM_INTERVAL 0x08
103
104/* Descriptor error interrupt */
105#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
106
107/* FIFO error interrupt */
108#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
109
110/* Buffer completion interrupt */
111#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
112
113#define SOF_HDA_CL_DMA_SD_INT_MASK \
114 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
115 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
116 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
117#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
118
119/* Intel HD Audio Code Loader DMA Registers */
120#define SOF_HDA_ADSP_LOADER_BASE 0x80
121#define SOF_HDA_ADSP_DPLBASE 0x70
122#define SOF_HDA_ADSP_DPUBASE 0x74
123#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
124
125/* Stream Registers */
126#define SOF_HDA_ADSP_REG_SD_CTL 0x00
127#define SOF_HDA_ADSP_REG_SD_STS 0x03
128#define SOF_HDA_ADSP_REG_SD_LPIB 0x04
129#define SOF_HDA_ADSP_REG_SD_CBL 0x08
130#define SOF_HDA_ADSP_REG_SD_LVI 0x0C
131#define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
132#define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
133#define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
134#define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
135#define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
136#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
137#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
138
139/* SDxFIFOS FIFOS */
140#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)
141
142/* CL: Software Position Based FIFO Capability Registers */
143#define SOF_DSP_REG_CL_SPBFIFO \
144 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
145#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
146#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
147#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
148#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
149
150/* Stream Number */
151#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
152#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
153 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
154 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
155
156#define HDA_DSP_HDA_BAR 0
157#define HDA_DSP_PP_BAR 1
158#define HDA_DSP_SPIB_BAR 2
159#define HDA_DSP_DRSM_BAR 3
160#define HDA_DSP_BAR 4
161
162#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
163
164#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
165
166#define HDA_DSP_PANIC_OFFSET(x) \
167 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
168
169/* SRAM window 0 FW "registers" */
170#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
171#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
172/* FW and ROM share offset 4 */
173#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
174#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
175#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
176
177#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
178
179#define HDA_DSP_STREAM_RESET_TIMEOUT 300
180/*
181 * Timeout in us, for setting the stream RUN bit, during
182 * start/stop the stream. The timeout expires if new RUN bit
183 * value cannot be read back within the specified time.
184 */
185#define HDA_DSP_STREAM_RUN_TIMEOUT 300
186
187#define HDA_DSP_SPIB_ENABLE 1
188#define HDA_DSP_SPIB_DISABLE 0
189
190#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
191
192#define HDA_DSP_STACK_DUMP_SIZE 32
193
194/* ROM/FW status register */
195#define FSR_STATE_MASK GENMASK(23, 0)
196#define FSR_WAIT_STATE_MASK GENMASK(27, 24)
197#define FSR_MODULE_MASK GENMASK(30, 28)
198#define FSR_HALTED BIT(31)
199#define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK)
200#define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24)
201#define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28)
202
203/* Wait states */
204#define FSR_WAIT_FOR_IPC_BUSY 0x1
205#define FSR_WAIT_FOR_IPC_DONE 0x2
206#define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
207#define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
208#define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
209#define FSR_WAIT_FOR_CSE_CSR 0x6
210
211/* Module codes */
212#define FSR_MOD_ROM 0x0
213#define FSR_MOD_ROM_BYP 0x1
214#define FSR_MOD_BASE_FW 0x2
215#define FSR_MOD_LP_BOOT 0x3
216#define FSR_MOD_BRNGUP 0x4
217#define FSR_MOD_ROM_EXT 0x5
218
219/* State codes (module dependent) */
220/* Module independent states */
221#define FSR_STATE_INIT 0x0
222#define FSR_STATE_INIT_DONE 0x1
223#define FSR_STATE_FW_ENTERED 0x5
224
225/* ROM states */
226#define FSR_STATE_ROM_INIT FSR_STATE_INIT
227#define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE
228#define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
229#define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
230#define FSR_STATE_ROM_FW_FW_LOADED 0x4
231#define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED
232#define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
233#define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
234#define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
235#define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
236#define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
237
238/* (ROM) CSE states */
239#define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
240#define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
241#define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
242#define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
243
244#define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
245#define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
246#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
247#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
248#define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
249
250/* BRINGUP (or BRNGUP) states */
251#define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT
252#define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE
253#define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
254#define FSR_STATE_BRINGUP_UNPACK_START 0X3
255#define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
256#define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED
257
258/* ROM status/error values */
259#define HDA_DSP_ROM_CSE_ERROR 40
260#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
261#define HDA_DSP_ROM_IMR_TO_SMALL 42
262#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
263#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
264#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
265#define HDA_DSP_ROM_L2_CACHE_ERROR 46
266#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
267#define HDA_DSP_ROM_API_PTR_INVALID 50
268#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
269#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
270#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
271#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
272#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
273#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
274#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
275
276#define HDA_DSP_ROM_IPC_CONTROL 0x01000000
277#define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
278
279/* various timeout values */
280#define HDA_DSP_PU_TIMEOUT 50
281#define HDA_DSP_PD_TIMEOUT 50
282#define HDA_DSP_RESET_TIMEOUT_US 50000
283#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
284#define HDA_DSP_INIT_TIMEOUT_US 500000
285#define HDA_DSP_CTRL_RESET_TIMEOUT 100
286#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
287#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
288#define HDA_DSP_REG_POLL_RETRY_COUNT 50
289
290#define HDA_DSP_ADSPIC_IPC BIT(0)
291#define HDA_DSP_ADSPIS_IPC BIT(0)
292
293/* Intel HD Audio General DSP Registers */
294#define HDA_DSP_GEN_BASE 0x0
295#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
296#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
297#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
298#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
299#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
300
301#define HDA_DSP_REG_ADSPIC2_SNDW BIT(5)
302#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
303
304/* Intel HD Audio Inter-Processor Communication Registers */
305#define HDA_DSP_IPC_BASE 0x40
306#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
307#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
308#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
309#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
310#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
311
312/* Intel Vendor Specific Registers */
313#define HDA_VS_INTEL_EM2 0x1030
314#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
315#define HDA_VS_INTEL_LTRP 0x1048
316#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
317
318/* HIPCI */
319#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
320#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
321
322/* HIPCIE */
323#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
324#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
325
326/* HIPCCTL */
327#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
328#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
329
330/* HIPCT */
331#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
332#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
333
334/* HIPCTE */
335#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
336
337#define HDA_DSP_ADSPIC_CL_DMA BIT(1)
338#define HDA_DSP_ADSPIS_CL_DMA BIT(1)
339
340/* Delay before scheduling D0i3 entry */
341#define BXT_D0I3_DELAY 5000
342
343#define FW_CL_STREAM_NUMBER 0x1
344#define HDA_FW_BOOT_ATTEMPTS 3
345
346/* ADSPCS - Audio DSP Control & Status */
347
348/*
349 * Core Reset - asserted high
350 * CRST Mask for a given core mask pattern, cm
351 */
352#define HDA_DSP_ADSPCS_CRST_SHIFT 0
353#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
354
355/*
356 * Core run/stall - when set to '1' core is stalled
357 * CSTALL Mask for a given core mask pattern, cm
358 */
359#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
360#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
361
362/*
363 * Set Power Active - when set to '1' turn cores on
364 * SPA Mask for a given core mask pattern, cm
365 */
366#define HDA_DSP_ADSPCS_SPA_SHIFT 16
367#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
368
369/*
370 * Current Power Active - power status of cores, set by hardware
371 * CPA Mask for a given core mask pattern, cm
372 */
373#define HDA_DSP_ADSPCS_CPA_SHIFT 24
374#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
375
376/*
377 * Mask for a given number of cores
378 * nc = number of supported cores
379 */
380#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
381
382/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
383#define CNL_DSP_IPC_BASE 0xc0
384#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
385#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
386#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
387#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
388#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
389#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
390#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
391
392/* HIPCI */
393#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
394#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
395
396/* HIPCIE */
397#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
398#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
399
400/* HIPCCTL */
401#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
402#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
403
404/* HIPCT */
405#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
406#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
407
408/* HIPCTDA */
409#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
410#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
411
412/* HIPCTDD */
413#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
414
415/* BDL */
416#define HDA_DSP_BDL_SIZE 4096
417#define HDA_DSP_MAX_BDL_ENTRIES \
418 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
419
420/* Number of DAIs */
421#define SOF_SKL_NUM_DAIS_NOCODEC 8
422
423#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
424#define SOF_SKL_NUM_DAIS 15
425#else
426#define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC
427#endif
428
429/* Intel HD Audio SRAM Window 0*/
430#define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
431#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
432
433/* Firmware status window */
434#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
435#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
436
437/* Host Device Memory Space */
438#define APL_SSP_BASE_OFFSET 0x2000
439#define CNL_SSP_BASE_OFFSET 0x10000
440
441/* Host Device Memory Size of a Single SSP */
442#define SSP_DEV_MEM_SIZE 0x1000
443
444/* SSP Count of the Platform */
445#define APL_SSP_COUNT 6
446#define CNL_SSP_COUNT 3
447#define ICL_SSP_COUNT 6
448#define TGL_SSP_COUNT 3
449#define MTL_SSP_COUNT 3
450
451/* SSP Registers */
452#define SSP_SSC1_OFFSET 0x4
453#define SSP_SET_SCLK_CONSUMER BIT(25)
454#define SSP_SET_SFRM_CONSUMER BIT(24)
455#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
456
457#define HDA_EXT_ADDR 0
458#define HDA_EXT_CODEC(x) ((x) & BIT(HDA_EXT_ADDR))
459#define HDA_IDISP_ADDR 2
460#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
461
462struct sof_intel_dsp_bdl {
463 __le32 addr_l;
464 __le32 addr_h;
465 __le32 size;
466 __le32 ioc;
467} __attribute((packed));
468
469#define SOF_HDA_PLAYBACK_STREAMS 16
470#define SOF_HDA_CAPTURE_STREAMS 16
471#define SOF_HDA_PLAYBACK 0
472#define SOF_HDA_CAPTURE 1
473
474/* stream flags */
475#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
476
477/*
478 * Time in ms for opportunistic D0I3 entry delay.
479 * This has been deliberately chosen to be long to avoid race conditions.
480 * Could be optimized in future.
481 */
482#define SOF_HDA_D0I3_WORK_DELAY_MS 5000
483
484/* HDA DSP D0 substate */
485enum sof_hda_D0_substate {
486 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
487 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
488};
489
490/* represents DSP HDA controller frontend - i.e. host facing control */
491struct sof_intel_hda_dev {
492 bool imrboot_supported;
493 bool skip_imr_boot;
494 bool booted_from_imr;
495
496 int boot_iteration;
497
498 /*
499 * DMA buffers for base firmware download. By default the buffers are
500 * allocated once and kept through the lifetime of the driver.
501 * See module parameter: persistent_cl_buffer
502 */
503 struct snd_dma_buffer cl_dmab;
504 bool cl_dmab_contains_basefw;
505 struct snd_dma_buffer iccmax_dmab;
506
507 struct hda_bus hbus;
508
509 /* hw config */
510 const struct sof_intel_dsp_desc *desc;
511
512 /* trace */
513 struct hdac_ext_stream *dtrace_stream;
514
515 /* if position update IPC needed */
516 u32 no_ipc_position;
517
518 /* the maximum number of streams (playback + capture) supported */
519 u32 stream_max;
520
521 /* PM related */
522 bool l1_disabled;/* is DMI link L1 disabled? */
523
524 /* DMIC device */
525 struct platform_device *dmic_dev;
526
527 /* delayed work to enter D0I3 opportunistically */
528 struct delayed_work d0i3_work;
529
530 /* ACPI information stored between scan and probe steps */
531 struct sdw_intel_acpi_info info;
532
533 /* sdw context allocated by SoundWire driver */
534 struct sdw_intel_ctx *sdw;
535
536 /* FW clock config, 0:HPRO, 1:LPRO */
537 bool clk_config_lpro;
538
539 wait_queue_head_t waitq;
540 bool code_loading;
541
542 /* Intel NHLT information */
543 struct nhlt_acpi_table *nhlt;
544
545 /*
546 * Pointing to the IPC message if immediate sending was not possible
547 * because the downlink communication channel was BUSY at the time.
548 * The message will be re-tried when the channel becomes free (the ACK
549 * is received from the DSP for the previous message)
550 */
551 struct snd_sof_ipc_msg *delayed_ipc_tx_msg;
552};
553
554static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
555{
556 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
557
558 return &hda->hbus.core;
559}
560
561static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
562{
563 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
564
565 return &hda->hbus;
566}
567
568struct sof_intel_hda_stream {
569 struct snd_sof_dev *sdev;
570 struct hdac_ext_stream hext_stream;
571 struct sof_intel_stream sof_intel_stream;
572 int host_reserved; /* reserve host DMA channel */
573 u32 flags;
574 struct completion ioc;
575};
576
577#define hstream_to_sof_hda_stream(hstream) \
578 container_of(hstream, struct sof_intel_hda_stream, hext_stream)
579
580#define bus_to_sof_hda(bus) \
581 container_of(bus, struct sof_intel_hda_dev, hbus.core)
582
583#define SOF_STREAM_SD_OFFSET(s) \
584 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
585 + SOF_HDA_ADSP_LOADER_BASE)
586
587#define SOF_STREAM_SD_OFFSET_CRST 0x1
588
589/*
590 * DAI support
591 */
592bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type);
593
594/*
595 * DSP Core services.
596 */
597int hda_dsp_probe_early(struct snd_sof_dev *sdev);
598int hda_dsp_probe(struct snd_sof_dev *sdev);
599void hda_dsp_remove(struct snd_sof_dev *sdev);
600void hda_dsp_remove_late(struct snd_sof_dev *sdev);
601int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
602int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
603int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
604int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
605 unsigned int core_mask);
606int hda_power_down_dsp(struct snd_sof_dev *sdev);
607int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
608void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
609void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
610bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask);
611
612int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
613 const struct sof_dsp_power_state *target_state);
614int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
615 const struct sof_dsp_power_state *target_state);
616
617int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
618int hda_dsp_resume(struct snd_sof_dev *sdev);
619int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
620int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
621int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
622int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev);
623int hda_dsp_shutdown(struct snd_sof_dev *sdev);
624int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
625void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
626void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
627void hda_ipc_dump(struct snd_sof_dev *sdev);
628void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
629void hda_dsp_d0i3_work(struct work_struct *work);
630int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
631bool hda_check_ipc_irq(struct snd_sof_dev *sdev);
632u32 hda_get_interface_mask(struct snd_sof_dev *sdev);
633
634/*
635 * DSP PCM Operations.
636 */
637u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
638u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
639int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
640 struct snd_pcm_substream *substream);
641int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
642 struct snd_pcm_substream *substream);
643int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
644 struct snd_pcm_substream *substream,
645 struct snd_pcm_hw_params *params,
646 struct snd_sof_platform_stream_params *platform_params);
647int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
648 struct snd_pcm_substream *substream);
649int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
650 struct snd_pcm_substream *substream, int cmd);
651snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
652 struct snd_pcm_substream *substream);
653int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
654
655/*
656 * DSP Stream Operations.
657 */
658
659int hda_dsp_stream_init(struct snd_sof_dev *sdev);
660void hda_dsp_stream_free(struct snd_sof_dev *sdev);
661int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
662 struct hdac_ext_stream *hext_stream,
663 struct snd_dma_buffer *dmab,
664 struct snd_pcm_hw_params *params);
665int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
666 struct hdac_ext_stream *hext_stream,
667 struct snd_dma_buffer *dmab,
668 struct snd_pcm_hw_params *params);
669int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
670 struct hdac_ext_stream *hext_stream, int cmd);
671irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
672int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
673 struct snd_dma_buffer *dmab,
674 struct hdac_stream *hstream);
675bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
676bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
677
678snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
679 int direction, bool can_sleep);
680u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev,
681 struct snd_soc_component *component,
682 struct snd_pcm_substream *substream);
683u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev,
684 struct snd_soc_component *component,
685 struct snd_pcm_substream *substream);
686
687struct hdac_ext_stream *
688 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
689int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
690int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
691 struct hdac_ext_stream *hext_stream,
692 int enable, u32 size);
693
694int hda_ipc_msg_data(struct snd_sof_dev *sdev,
695 struct snd_sof_pcm_stream *sps,
696 void *p, size_t sz);
697int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
698 struct snd_sof_pcm_stream *sps,
699 size_t posn_offset);
700
701/*
702 * DSP IPC Operations.
703 */
704int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
705 struct snd_sof_ipc_msg *msg);
706void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
707int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
708int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
709
710irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
711int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
712
713void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level);
714void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
715 u32 flags);
716
717/*
718 * DSP Code loader.
719 */
720int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
721int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
722int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
723
724struct hdac_ext_stream *hda_cl_prepare(struct device *dev, unsigned int format,
725 unsigned int size, struct snd_dma_buffer *dmab,
726 bool persistent_buffer, int direction,
727 bool is_iccmax);
728int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd);
729
730int hda_cl_cleanup(struct device *dev, struct snd_dma_buffer *dmab,
731 bool persistent_buffer, struct hdac_ext_stream *hext_stream);
732int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
733#define HDA_CL_STREAM_FORMAT 0x40
734
735/* pre and post fw run ops */
736int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
737int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
738
739/* parse platform specific ext manifest ops */
740int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
741 const struct sof_ext_man_elem_header *hdr);
742
743/*
744 * HDA Controller Operations.
745 */
746int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
747void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
748void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
749int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
750void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
751int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
752int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev);
753void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
754/*
755 * HDA bus operations.
756 */
757void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev);
758void sof_hda_bus_exit(struct snd_sof_dev *sdev);
759
760#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
761/*
762 * HDA Codec operations.
763 */
764void hda_codec_probe_bus(struct snd_sof_dev *sdev);
765void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
766void hda_codec_jack_check(struct snd_sof_dev *sdev);
767void hda_codec_check_for_state_change(struct snd_sof_dev *sdev);
768void hda_codec_init_cmd_io(struct snd_sof_dev *sdev);
769void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev);
770void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev);
771void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev);
772void hda_codec_detect_mask(struct snd_sof_dev *sdev);
773void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev);
774bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev);
775void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status);
776void hda_codec_device_remove(struct snd_sof_dev *sdev);
777
778#else
779
780static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { }
781static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { }
782static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { }
783static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { }
784static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { }
785static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { }
786static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { }
787static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { }
788static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { }
789static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { }
790static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; }
791static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { }
792static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { }
793
794#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
795
796#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
797
798void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
799int hda_codec_i915_init(struct snd_sof_dev *sdev);
800int hda_codec_i915_exit(struct snd_sof_dev *sdev);
801
802#else
803
804static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { }
805static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
806static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
807
808#endif
809
810/*
811 * Trace Control.
812 */
813int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
814 struct sof_ipc_dma_trace_params_ext *dtrace_params);
815int hda_dsp_trace_release(struct snd_sof_dev *sdev);
816int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
817
818/*
819 * SoundWire support
820 */
821#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
822
823int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev);
824int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev);
825int hda_sdw_check_lcount(struct snd_sof_dev *sdev);
826int hda_sdw_startup(struct snd_sof_dev *sdev);
827void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable);
828void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
829bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev);
830void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev);
831void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
832bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
833
834#else
835
836static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
837{
838 return 0;
839}
840
841static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
842{
843 return 0;
844}
845
846static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
847{
848 return 0;
849}
850
851static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
852{
853 return 0;
854}
855
856static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
857{
858}
859
860static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
861{
862}
863
864static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
865{
866 return false;
867}
868
869static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev)
870{
871}
872
873static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
874{
875}
876
877static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
878{
879 return false;
880}
881
882#endif
883
884int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream,
885 struct snd_pcm_hw_params *params,
886 struct snd_soc_dai *cpu_dai,
887 int link_id,
888 int intel_alh_id);
889
890int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream,
891 struct snd_soc_dai *cpu_dai,
892 int link_id);
893
894int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd,
895 struct snd_soc_dai *cpu_dai);
896
897/* common dai driver */
898extern struct snd_soc_dai_driver skl_dai[];
899int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
900
901/*
902 * Platform Specific HW abstraction Ops.
903 */
904extern const struct snd_sof_dsp_ops sof_hda_common_ops;
905
906extern struct snd_sof_dsp_ops sof_skl_ops;
907int sof_skl_ops_init(struct snd_sof_dev *sdev);
908extern struct snd_sof_dsp_ops sof_apl_ops;
909int sof_apl_ops_init(struct snd_sof_dev *sdev);
910extern struct snd_sof_dsp_ops sof_cnl_ops;
911int sof_cnl_ops_init(struct snd_sof_dev *sdev);
912extern struct snd_sof_dsp_ops sof_tgl_ops;
913int sof_tgl_ops_init(struct snd_sof_dev *sdev);
914extern struct snd_sof_dsp_ops sof_icl_ops;
915int sof_icl_ops_init(struct snd_sof_dev *sdev);
916extern struct snd_sof_dsp_ops sof_mtl_ops;
917int sof_mtl_ops_init(struct snd_sof_dev *sdev);
918extern struct snd_sof_dsp_ops sof_lnl_ops;
919int sof_lnl_ops_init(struct snd_sof_dev *sdev);
920
921extern const struct sof_intel_dsp_desc skl_chip_info;
922extern const struct sof_intel_dsp_desc apl_chip_info;
923extern const struct sof_intel_dsp_desc cnl_chip_info;
924extern const struct sof_intel_dsp_desc icl_chip_info;
925extern const struct sof_intel_dsp_desc tgl_chip_info;
926extern const struct sof_intel_dsp_desc tglh_chip_info;
927extern const struct sof_intel_dsp_desc ehl_chip_info;
928extern const struct sof_intel_dsp_desc jsl_chip_info;
929extern const struct sof_intel_dsp_desc adls_chip_info;
930extern const struct sof_intel_dsp_desc mtl_chip_info;
931extern const struct sof_intel_dsp_desc arl_s_chip_info;
932extern const struct sof_intel_dsp_desc lnl_chip_info;
933extern const struct sof_intel_dsp_desc ptl_chip_info;
934
935/* Probes support */
936#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
937int hda_probes_register(struct snd_sof_dev *sdev);
938void hda_probes_unregister(struct snd_sof_dev *sdev);
939#else
940static inline int hda_probes_register(struct snd_sof_dev *sdev)
941{
942 return 0;
943}
944
945static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
946{
947}
948#endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
949
950/* SOF client registration for HDA platforms */
951int hda_register_clients(struct snd_sof_dev *sdev);
952void hda_unregister_clients(struct snd_sof_dev *sdev);
953
954/* machine driver select */
955struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
956void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
957 struct snd_sof_dev *sdev);
958
959/* PCI driver selection and probe */
960int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
961
962struct snd_sof_dai;
963struct sof_ipc_dai_config;
964
965#define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */
966#define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */
967#define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */
968
969extern int sof_hda_position_quirk;
970
971void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
972void hda_ops_free(struct snd_sof_dev *sdev);
973
974/* SKL/KBL */
975int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
976int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
977
978/* IPC4 */
979irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
980int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
981irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
982bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev);
983void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev,
984 struct snd_sof_ipc_msg *msg);
985int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
986void hda_ipc4_dump(struct snd_sof_dev *sdev);
987extern struct sdw_intel_ops sdw_callback;
988
989struct sof_ipc4_fw_library;
990int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
991 struct sof_ipc4_fw_library *fw_lib, bool reload);
992
993/**
994 * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise
995 * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream
996 * @assign_hext_stream: Function pointer to assign a hdac_ext_stream
997 * @release_hext_stream: Function pointer to release the hdac_ext_stream
998 * @setup_hext_stream: Function pointer for hdac_ext_stream setup
999 * @reset_hext_stream: Function pointer for hdac_ext_stream reset
1000 * @pre_trigger: Function pointer for DAI DMA pre-trigger actions
1001 * @trigger: Function pointer for DAI DMA trigger actions
1002 * @post_trigger: Function pointer for DAI DMA post-trigger actions
1003 * @codec_dai_set_stream: Function pointer to set codec-side stream information
1004 * @calc_stream_format: Function pointer to determine stream format from hw_params and
1005 * for HDaudio codec DAI from the .sig bits
1006 * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV
1007 * for legacy HDaudio links or program HDaudio Extended Link registers.
1008 */
1009struct hda_dai_widget_dma_ops {
1010 struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev,
1011 struct snd_soc_dai *cpu_dai,
1012 struct snd_pcm_substream *substream);
1013 struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev,
1014 struct snd_soc_dai *cpu_dai,
1015 struct snd_pcm_substream *substream);
1016 void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1017 struct snd_pcm_substream *substream);
1018 void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
1019 unsigned int format_val);
1020 void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream);
1021 int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1022 struct snd_pcm_substream *substream, int cmd);
1023 int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1024 struct snd_pcm_substream *substream, int cmd);
1025 int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1026 struct snd_pcm_substream *substream, int cmd);
1027 void (*codec_dai_set_stream)(struct snd_sof_dev *sdev,
1028 struct snd_pcm_substream *substream,
1029 struct hdac_stream *hstream);
1030 unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev,
1031 struct snd_pcm_substream *substream,
1032 struct snd_pcm_hw_params *params);
1033 struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev,
1034 struct snd_pcm_substream *substream);
1035};
1036
1037const struct hda_dai_widget_dma_ops *
1038hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget);
1039int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags,
1040 struct snd_sof_dai_config_data *data);
1041
1042static inline struct snd_sof_dev *widget_to_sdev(struct snd_soc_dapm_widget *w)
1043{
1044 struct snd_sof_widget *swidget = w->dobj.private;
1045 struct snd_soc_component *component = swidget->scomp;
1046
1047 return snd_soc_component_get_drvdata(component);
1048}
1049
1050#endif