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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16#include <linux/phylink.h>
17
18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
20#define STMMAC_CH_MAX 8
21
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */
37#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */
38#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */
39
40/* MTL algorithms identifiers */
41#define MTL_TX_ALGORITHM_WRR 0x0
42#define MTL_TX_ALGORITHM_WFQ 0x1
43#define MTL_TX_ALGORITHM_DWRR 0x2
44#define MTL_TX_ALGORITHM_SP 0x3
45#define MTL_RX_ALGORITHM_SP 0x4
46#define MTL_RX_ALGORITHM_WSP 0x5
47
48/* RX/TX Queue Mode */
49#define MTL_QUEUE_AVB 0x0
50#define MTL_QUEUE_DCB 0x1
51
52/* The MDC clock could be set higher than the IEEE 802.3
53 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
54 * of value different than the above defined values. The resultant MDIO
55 * clock frequency of 12.5 MHz is applicable for the interfacing chips
56 * supporting higher MDC clocks.
57 * The MDC clock selection macros need to be defined for MDC clock rate
58 * of 12.5 MHz, corresponding to the following selection.
59 */
60#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
61#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
62#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
63#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
64#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
65#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
66#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
67#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
68
69/* AXI DMA Burst length supported */
70#define DMA_AXI_BLEN_4 (1 << 1)
71#define DMA_AXI_BLEN_8 (1 << 2)
72#define DMA_AXI_BLEN_16 (1 << 3)
73#define DMA_AXI_BLEN_32 (1 << 4)
74#define DMA_AXI_BLEN_64 (1 << 5)
75#define DMA_AXI_BLEN_128 (1 << 6)
76#define DMA_AXI_BLEN_256 (1 << 7)
77#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
78 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
79 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
80
81struct stmmac_priv;
82
83/* Platfrom data for platform device structure's platform_data field */
84
85struct stmmac_mdio_bus_data {
86 unsigned int phy_mask;
87 unsigned int pcs_mask;
88 unsigned int default_an_inband;
89 int *irqs;
90 int probed_phy_irq;
91 bool needs_reset;
92};
93
94struct stmmac_dma_cfg {
95 int pbl;
96 int txpbl;
97 int rxpbl;
98 bool pblx8;
99 int fixed_burst;
100 int mixed_burst;
101 bool aal;
102 bool eame;
103 bool multi_msi_en;
104 bool dche;
105 bool atds;
106};
107
108#define AXI_BLEN 7
109struct stmmac_axi {
110 bool axi_lpi_en;
111 bool axi_xit_frm;
112 u32 axi_wr_osr_lmt;
113 u32 axi_rd_osr_lmt;
114 bool axi_kbbe;
115 u32 axi_blen[AXI_BLEN];
116 bool axi_fb;
117 bool axi_mb;
118 bool axi_rb;
119};
120
121struct stmmac_rxq_cfg {
122 u8 mode_to_use;
123 u32 chan;
124 u8 pkt_route;
125 bool use_prio;
126 u32 prio;
127};
128
129struct stmmac_txq_cfg {
130 u32 weight;
131 bool coe_unsupported;
132 u8 mode_to_use;
133 /* Credit Base Shaper parameters */
134 u32 send_slope;
135 u32 idle_slope;
136 u32 high_credit;
137 u32 low_credit;
138 bool use_prio;
139 u32 prio;
140 int tbs_en;
141};
142
143struct stmmac_safety_feature_cfg {
144 u32 tsoee;
145 u32 mrxpee;
146 u32 mestee;
147 u32 mrxee;
148 u32 mtxee;
149 u32 epsi;
150 u32 edpp;
151 u32 prtyen;
152 u32 tmouten;
153};
154
155/* Addresses that may be customized by a platform */
156struct dwmac4_addrs {
157 u32 dma_chan;
158 u32 dma_chan_offset;
159 u32 mtl_chan;
160 u32 mtl_chan_offset;
161 u32 mtl_ets_ctrl;
162 u32 mtl_ets_ctrl_offset;
163 u32 mtl_txq_weight;
164 u32 mtl_txq_weight_offset;
165 u32 mtl_send_slp_cred;
166 u32 mtl_send_slp_cred_offset;
167 u32 mtl_high_cred;
168 u32 mtl_high_cred_offset;
169 u32 mtl_low_cred;
170 u32 mtl_low_cred_offset;
171};
172
173#define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
174#define STMMAC_FLAG_SPH_DISABLE BIT(1)
175#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
176#define STMMAC_FLAG_HAS_SUN8I BIT(3)
177#define STMMAC_FLAG_TSO_EN BIT(4)
178#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
179#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
180#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
181#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
182#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
183#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
184#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
185#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
186
187struct plat_stmmacenet_data {
188 int bus_id;
189 int phy_addr;
190 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
191 * ^ ^
192 * mac_interface phy_interface
193 *
194 * mac_interface is the MAC-side interface, which may be the same
195 * as phy_interface if there is no intervening PCS. If there is a
196 * PCS, then mac_interface describes the interface mode between the
197 * MAC and PCS, and phy_interface describes the interface mode
198 * between the PCS and PHY.
199 */
200 phy_interface_t mac_interface;
201 /* phy_interface is the PHY-side interface - the interface used by
202 * an attached PHY.
203 */
204 phy_interface_t phy_interface;
205 struct stmmac_mdio_bus_data *mdio_bus_data;
206 struct device_node *phy_node;
207 struct fwnode_handle *port_node;
208 struct device_node *mdio_node;
209 struct stmmac_dma_cfg *dma_cfg;
210 struct stmmac_safety_feature_cfg *safety_feat_cfg;
211 int clk_csr;
212 int has_gmac;
213 int enh_desc;
214 int tx_coe;
215 int rx_coe;
216 int bugged_jumbo;
217 int pmt;
218 int force_sf_dma_mode;
219 int force_thresh_dma_mode;
220 int riwt_off;
221 int max_speed;
222 int maxmtu;
223 int multicast_filter_bins;
224 int unicast_filter_entries;
225 int tx_fifo_size;
226 int rx_fifo_size;
227 u32 host_dma_width;
228 u32 rx_queues_to_use;
229 u32 tx_queues_to_use;
230 u8 rx_sched_algorithm;
231 u8 tx_sched_algorithm;
232 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
233 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
234 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
235 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
236 int (*serdes_powerup)(struct net_device *ndev, void *priv);
237 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
238 void (*speed_mode_2500)(struct net_device *ndev, void *priv);
239 void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
240 int (*init)(struct platform_device *pdev, void *priv);
241 void (*exit)(struct platform_device *pdev, void *priv);
242 struct mac_device_info *(*setup)(void *priv);
243 int (*clks_config)(void *priv, bool enabled);
244 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
245 void *ctx);
246 void (*dump_debug_regs)(void *priv);
247 int (*pcs_init)(struct stmmac_priv *priv);
248 void (*pcs_exit)(struct stmmac_priv *priv);
249 struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
250 phy_interface_t interface);
251 void *bsp_priv;
252 struct clk *stmmac_clk;
253 struct clk *pclk;
254 struct clk *clk_ptp_ref;
255 unsigned long clk_ptp_rate;
256 unsigned long clk_ref_rate;
257 unsigned int mult_fact_100ns;
258 s32 ptp_max_adj;
259 u32 cdc_error_adj;
260 struct reset_control *stmmac_rst;
261 struct reset_control *stmmac_ahb_rst;
262 struct stmmac_axi *axi;
263 int has_gmac4;
264 int rss_en;
265 int mac_port_sel_speed;
266 int has_xgmac;
267 u8 vlan_fail_q;
268 unsigned long eee_usecs_rate;
269 struct pci_dev *pdev;
270 int int_snapshot_num;
271 int msi_mac_vec;
272 int msi_wol_vec;
273 int msi_lpi_vec;
274 int msi_sfty_ce_vec;
275 int msi_sfty_ue_vec;
276 int msi_rx_base_vec;
277 int msi_tx_base_vec;
278 const struct dwmac4_addrs *dwmac4_addrs;
279 unsigned int flags;
280};
281#endif