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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
27#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28
29struct drm_crtc;
30struct dm_crtc_state;
31
32enum amdgpu_dm_pipe_crc_source {
33 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
34 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
35 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
36 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
37 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
38 AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
39 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
40};
41
42#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
43#define MAX_CRTC 6
44
45enum secure_display_mode {
46 /* via dmub + psp */
47 LEGACY_MODE = 0,
48 /* driver directly */
49 DISPLAY_CRC_MODE,
50 SECURE_DISPLAY_MODE_MAX,
51};
52
53struct phy_id_mapping {
54 bool assigned;
55 bool is_mst;
56 uint8_t enc_hw_inst;
57 u8 lct;
58 u8 port_num;
59 u8 rad[8];
60};
61
62struct crc_data {
63 uint32_t crc_R;
64 uint32_t crc_G;
65 uint32_t crc_B;
66 uint32_t frame_count;
67 bool crc_ready;
68};
69
70struct crc_info {
71 struct crc_data crc[MAX_CRC_WINDOW_NUM];
72 struct completion completion;
73 spinlock_t lock;
74};
75
76struct crc_window_param {
77 uint16_t x_start;
78 uint16_t y_start;
79 uint16_t x_end;
80 uint16_t y_end;
81 /* CRC window is activated or not*/
82 bool enable;
83 /* Update crc window during vertical blank or not */
84 bool update_win;
85 /* skip reading/writing for few frames */
86 int skip_frame_cnt;
87};
88
89struct secure_display_crtc_context {
90 /* work to notify PSP TA*/
91 struct work_struct notify_ta_work;
92
93 /* work to forward ROI to dmcu/dmub */
94 struct work_struct forward_roi_work;
95
96 struct drm_crtc *crtc;
97
98 /* Region of Interest (ROI) */
99 struct crc_window roi[MAX_CRC_WINDOW_NUM];
100
101 struct crc_info crc_info;
102};
103
104struct secure_display_context {
105
106 struct secure_display_crtc_context *crtc_ctx;
107 /* Whether dmub support multiple ROI setting */
108 bool support_mul_roi;
109 enum secure_display_mode op_mode;
110 bool phy_mapping_updated;
111 int phy_id_mapping_cnt;
112 struct phy_id_mapping phy_id_mapping[MAX_CRTC];
113};
114#endif
115
116static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
117{
118 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
119 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
120}
121
122/* amdgpu_dm_crc.c */
123#ifdef CONFIG_DEBUG_FS
124int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
125 struct dm_crtc_state *dm_crtc_state,
126 enum amdgpu_dm_pipe_crc_source source);
127int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
128int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
129 const char *src_name,
130 size_t *values_cnt);
131const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
132 size_t *count);
133void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
134#else
135#define amdgpu_dm_crtc_set_crc_source NULL
136#define amdgpu_dm_crtc_verify_crc_source NULL
137#define amdgpu_dm_crtc_get_crc_sources NULL
138#define amdgpu_dm_crtc_handle_crc_irq(x)
139#endif
140
141#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
142bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
143void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
144void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev);
145#else
146#define amdgpu_dm_crc_window_is_activated(x)
147#define amdgpu_dm_crtc_handle_crc_window_irq(x)
148#define amdgpu_dm_crtc_secure_display_create_contexts(x)
149#endif
150
151#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */