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1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2/*
3 * Author: Hanlu Li <lihanlu@loongson.cn>
4 * Huacai Chen <chenhuacai@loongson.cn>
5 *
6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 */
8#ifndef _UAPI_ASM_PTRACE_H
9#define _UAPI_ASM_PTRACE_H
10
11#include <linux/types.h>
12
13#ifndef __KERNEL__
14#include <stdint.h>
15#endif
16
17/*
18 * For PTRACE_{POKE,PEEK}USR. 0 - 31 are GPRs,
19 * 32 is syscall's original ARG0, 33 is PC, 34 is BADVADDR.
20 */
21#define GPR_BASE 0
22#define GPR_NUM 32
23#define GPR_END (GPR_BASE + GPR_NUM - 1)
24#define ARG0 (GPR_END + 1)
25#define PC (GPR_END + 2)
26#define BADVADDR (GPR_END + 3)
27
28#define NUM_FPU_REGS 32
29
30struct user_pt_regs {
31 /* Main processor registers. */
32 unsigned long regs[32];
33
34 /* Original syscall arg0. */
35 unsigned long orig_a0;
36
37 /* Special CSR registers. */
38 unsigned long csr_era;
39 unsigned long csr_badv;
40 unsigned long reserved[10];
41} __attribute__((aligned(8)));
42
43struct user_fp_state {
44 uint64_t fpr[32];
45 uint64_t fcc;
46 uint32_t fcsr;
47};
48
49struct user_lsx_state {
50 /* 32 registers, 128 bits width per register. */
51 uint64_t vregs[32*2];
52};
53
54struct user_lasx_state {
55 /* 32 registers, 256 bits width per register. */
56 uint64_t vregs[32*4];
57};
58
59struct user_lbt_state {
60 uint64_t scr[4];
61 uint32_t eflags;
62 uint32_t ftop;
63};
64
65struct user_watch_state {
66 uint64_t dbg_info;
67 struct {
68 uint64_t addr;
69 uint64_t mask;
70 uint32_t ctrl;
71 uint32_t pad;
72 } dbg_regs[8];
73};
74
75struct user_watch_state_v2 {
76 uint64_t dbg_info;
77 struct {
78 uint64_t addr;
79 uint64_t mask;
80 uint32_t ctrl;
81 uint32_t pad;
82 } dbg_regs[14];
83};
84
85#define PTRACE_SYSEMU 0x1f
86#define PTRACE_SYSEMU_SINGLESTEP 0x20
87
88#endif /* _UAPI_ASM_PTRACE_H */