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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8
9#ifndef __ASM_SYSREG_H
10#define __ASM_SYSREG_H
11
12#include <linux/bits.h>
13#include <linux/stringify.h>
14#include <linux/kasan-tags.h>
15
16#include <asm/gpr-num.h>
17
18/*
19 * ARMv8 ARM reserves the following encoding for system registers:
20 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21 * C5.2, version:ARM DDI 0487A.f)
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
27 */
28#define Op0_shift 19
29#define Op0_mask 0x3
30#define Op1_shift 16
31#define Op1_mask 0x7
32#define CRn_shift 12
33#define CRn_mask 0xf
34#define CRm_shift 8
35#define CRm_mask 0xf
36#define Op2_shift 5
37#define Op2_mask 0x7
38
39#define sys_reg(op0, op1, crn, crm, op2) \
40 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 ((op2) << Op2_shift))
43
44#define sys_insn sys_reg
45
46#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
47#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
48#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
49#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
50#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
51
52#ifndef CONFIG_BROKEN_GAS_INST
53
54#ifdef __ASSEMBLY__
55// The space separator is omitted so that __emit_inst(x) can be parsed as
56// either an assembler directive or an assembler macro argument.
57#define __emit_inst(x) .inst(x)
58#else
59#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
60#endif
61
62#else /* CONFIG_BROKEN_GAS_INST */
63
64#ifndef CONFIG_CPU_BIG_ENDIAN
65#define __INSTR_BSWAP(x) (x)
66#else /* CONFIG_CPU_BIG_ENDIAN */
67#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
70 (((x) >> 24) & 0x000000ff))
71#endif /* CONFIG_CPU_BIG_ENDIAN */
72
73#ifdef __ASSEMBLY__
74#define __emit_inst(x) .long __INSTR_BSWAP(x)
75#else /* __ASSEMBLY__ */
76#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77#endif /* __ASSEMBLY__ */
78
79#endif /* CONFIG_BROKEN_GAS_INST */
80
81/*
82 * Instructions for modifying PSTATE fields.
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85 * for accessing PSTATE fields have the following encoding:
86 * Op0 = 0, CRn = 4
87 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88 * CRm = Imm4 for the instruction.
89 * Rt = 0x1f
90 */
91#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
92#define PSTATE_Imm_shift CRm_shift
93#define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
94
95#define PSTATE_PAN pstate_field(0, 4)
96#define PSTATE_UAO pstate_field(0, 3)
97#define PSTATE_SSBS pstate_field(3, 1)
98#define PSTATE_DIT pstate_field(3, 2)
99#define PSTATE_TCO pstate_field(3, 4)
100
101#define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN)
102#define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO)
103#define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS)
104#define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT)
105#define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO)
106
107#define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
108#define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
109#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
110#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
111
112/* Register-based PAN access, for save/restore purposes */
113#define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
114
115#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
116 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
117
118#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
119
120#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
121#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
122#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
123#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
124#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
125#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
126#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
129
130#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
131#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
132#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
133
134#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
135#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
136#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
137
138#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
139#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
140#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
141
142#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
143
144#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
145#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
146#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
147
148#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
149#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
150#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
151
152#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
153#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
154#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
155
156/* Data cache zero operations */
157#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
160
161/*
162 * Automatically generated definitions for system registers, the
163 * manual encodings below are in the process of being converted to
164 * come from here. The header relies on the definition of sys_reg()
165 * earlier in this file.
166 */
167#include "asm/sysreg-defs.h"
168
169/*
170 * System registers, organised loosely by encoding but grouped together
171 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
172 */
173#define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
174#define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
175#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
176
177#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
178#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
179#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
180#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
181#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
182
183#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
184#define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
185#define OSLSR_EL1_OSLM_NI 0
186#define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
187#define OSLSR_EL1_OSLK BIT(1)
188
189#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
190#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
191#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
194#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
195#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
196#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
199
200#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
201#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
202#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
203#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
204#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
205#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
206#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
207
208#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
209#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
210#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
211
212#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
216#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
228#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
230#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
249#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
250#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
260#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
269#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
272
273/* ETM */
274#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
275
276#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
277
278#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
279#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
280#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
281
282#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
283#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
284#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
285
286#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
287
288#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
289#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
290#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
291#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
292
293#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
294#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
295#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
296#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
297
298#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
299#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
300
301#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
302#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
303
304#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
305
306#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
307#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
308#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
309
310#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
311#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
312#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
313#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
314#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
315#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
316#define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
317#define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
318#define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
319#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
320#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
321#define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
322#define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
323#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
324#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
325
326#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
327
328#define SYS_PAR_EL1_F BIT(0)
329/* When PAR_EL1.F == 1 */
330#define SYS_PAR_EL1_FST GENMASK(6, 1)
331#define SYS_PAR_EL1_PTW BIT(8)
332#define SYS_PAR_EL1_S BIT(9)
333#define SYS_PAR_EL1_AssuredOnly BIT(12)
334#define SYS_PAR_EL1_TopLevel BIT(13)
335#define SYS_PAR_EL1_Overlay BIT(14)
336#define SYS_PAR_EL1_DirtyBit BIT(15)
337#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)
338#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
339#define SYS_PAR_EL1_RES1 BIT(11)
340/* When PAR_EL1.F == 0 */
341#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
342#define SYS_PAR_EL1_NS BIT(9)
343#define SYS_PAR_EL1_F0_IMPDEF BIT(10)
344#define SYS_PAR_EL1_NSE BIT(11)
345#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)
346#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
347#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
348
349/*** Statistical Profiling Extension ***/
350#define PMSEVFR_EL1_RES0_IMP \
351 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
352 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
353#define PMSEVFR_EL1_RES0_V1P1 \
354 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
355#define PMSEVFR_EL1_RES0_V1P2 \
356 (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
357
358/* Buffer error reporting */
359#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
360#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
361
362#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
363#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
364
365#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
366
367/*** End of Statistical Profiling Extension ***/
368
369#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
370#define TRBSR_EL1_BSC_SHIFT 0
371
372#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
374
375#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
376
377#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
378#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
379
380#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
381#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
382
383#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
384#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
385#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
386#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
387#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
388#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
389#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
390#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
391#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
392#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
393#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
394#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
395#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
396#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
397#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
398#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
399#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
400#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
401#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
402#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
403#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
404#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
405#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
406#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
407#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
408#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
409#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
410
411#define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
412
413#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
414
415#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
416
417#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
418#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
419
420#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
421#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
422#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
423#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
424#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
425#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
426#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
427#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
428#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
429#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
430#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
431#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
432
433#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
434#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
435#define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
436
437#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
438
439/* Definitions for system register interface to AMU for ARMv8.4 onwards */
440#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
441#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
442#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
443#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
444#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
445#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
446#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
447#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
448#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
449
450/*
451 * Group 0 of activity monitors (architected):
452 * op0 op1 CRn CRm op2
453 * Counter: 11 011 1101 010:n<3> n<2:0>
454 * Type: 11 011 1101 011:n<3> n<2:0>
455 * n: 0-15
456 *
457 * Group 1 of activity monitors (auxiliary):
458 * op0 op1 CRn CRm op2
459 * Counter: 11 011 1101 110:n<3> n<2:0>
460 * Type: 11 011 1101 111:n<3> n<2:0>
461 * n: 0-15
462 */
463
464#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
465#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
466#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
467#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
468
469/* AMU v1: Fixed (architecturally defined) activity monitors */
470#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
471#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
472#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
473#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
474
475#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
476
477#define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
478#define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
479#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
480#define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
481
482#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
483#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
484#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
485
486#define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
487#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
488#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
489
490#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
491#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
492#define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
493#define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
494#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
495#define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
496#define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
497
498#define __PMEV_op2(n) ((n) & 0x7)
499#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
500#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
501#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
502#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
503
504#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
505
506#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
507#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
508
509#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
510#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
511#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
512#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
513#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
514#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
515#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
516#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
517
518#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
519#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
520#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
521#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
522#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
523
524#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
525#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
526#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
527#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
528#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
529#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
530#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
531#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
532#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
533#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
534#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
535#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
536#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
537#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
538#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
539#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
540
541#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
542#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
543
544#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
545#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
546
547#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
548#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
549#define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
550#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
551#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
552#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
553#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
554#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
555#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
556
557#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
558#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
559#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
560#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
561#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
562
563#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
564#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
565#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
566#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
567#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
568#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
569#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
570#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
571
572#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
573#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
574#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
575#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
576#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
577#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
578#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
579#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
580#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
581
582#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
583#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
584#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
585#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
586#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
587#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
588#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
589#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
590#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
591
592#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
593#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
594#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
595
596#define __AMEV_op2(m) (m & 0x7)
597#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
598#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
599#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
600#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
601#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
602
603#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
604#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
605#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
606#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
607#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
608#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
609#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
610#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
611
612/* VHE encodings for architectural EL0/1 system registers */
613#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
614#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
615#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
616#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
617#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
618#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
619#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
620#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
621#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
622#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
623#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
624#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
625#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
626#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
627#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
628#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
629#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
630#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
631#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
632#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
633#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
634#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
635#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
636#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
637#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
638#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
639#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
640#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
641#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
642#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
643#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
644
645#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
646
647/* AT instructions */
648#define AT_Op0 1
649#define AT_CRn 7
650
651#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
652#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
653#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
654#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
655#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
656#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
657#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
658#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
659#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
660#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
661#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
662#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
663#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
664#define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
665
666/* TLBI instructions */
667#define TLBI_Op0 1
668
669#define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
670#define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */
671
672#define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
673#define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
674
675#define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
676#define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
677#define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
678#define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
679#define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
680#define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
681#define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
682#define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
683
684#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
685#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
686#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
687#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
688#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
689#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
690#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
691#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
692#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
693#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
694#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
695#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
696#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
697#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
698#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
699#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
700#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
701#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
702#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
703#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
704#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
705#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
706#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
707#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
708#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
709#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
710#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
711#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
712#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
713#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
714#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
715#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
716#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
717#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
718#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
719#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
720#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
721#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
722#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
723#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
724#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
725#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
726#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
727#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
728#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
729#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
730#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
731#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
732#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
733#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
734#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
735#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
736#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
737#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
738#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
739#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
740#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
741#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
742#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
743#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
744#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
745#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
746#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
747#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
748#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
749#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
750#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
751#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
752#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
753#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
754#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
755#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
756#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
757#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
758#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
759#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
760#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
761#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
762#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
763#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
764#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
765#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
766#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
767#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
768#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
769#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
770#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
771#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
772#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
773#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
774#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
775#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
776#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
777#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
778#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
779#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
780#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
781#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
782#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
783#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
784#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
785#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
786#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
787#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
788#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
789#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
790#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
791#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
792#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
793#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
794#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
795#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
796#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
797#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
798#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
799#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
800#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
801#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
802#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
803#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
804#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
805#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
806#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
807#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
808#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
809#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
810
811/* Misc instructions */
812#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
813#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
814#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
815#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
816
817#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
818#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
819#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
820#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
821#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
822#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
823
824/* Common SCTLR_ELx flags. */
825#define SCTLR_ELx_ENTP2 (BIT(60))
826#define SCTLR_ELx_DSSBS (BIT(44))
827#define SCTLR_ELx_ATA (BIT(43))
828
829#define SCTLR_ELx_EE_SHIFT 25
830#define SCTLR_ELx_ENIA_SHIFT 31
831
832#define SCTLR_ELx_ITFSB (BIT(37))
833#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
834#define SCTLR_ELx_ENIB (BIT(30))
835#define SCTLR_ELx_LSMAOE (BIT(29))
836#define SCTLR_ELx_nTLSMD (BIT(28))
837#define SCTLR_ELx_ENDA (BIT(27))
838#define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
839#define SCTLR_ELx_EIS (BIT(22))
840#define SCTLR_ELx_IESB (BIT(21))
841#define SCTLR_ELx_TSCXT (BIT(20))
842#define SCTLR_ELx_WXN (BIT(19))
843#define SCTLR_ELx_ENDB (BIT(13))
844#define SCTLR_ELx_I (BIT(12))
845#define SCTLR_ELx_EOS (BIT(11))
846#define SCTLR_ELx_SA (BIT(3))
847#define SCTLR_ELx_C (BIT(2))
848#define SCTLR_ELx_A (BIT(1))
849#define SCTLR_ELx_M (BIT(0))
850
851/* SCTLR_EL2 specific flags. */
852#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
853 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
854 (BIT(29)))
855
856#define SCTLR_EL2_BT (BIT(36))
857#ifdef CONFIG_CPU_BIG_ENDIAN
858#define ENDIAN_SET_EL2 SCTLR_ELx_EE
859#else
860#define ENDIAN_SET_EL2 0
861#endif
862
863#define INIT_SCTLR_EL2_MMU_ON \
864 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
865 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \
866 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
867
868#define INIT_SCTLR_EL2_MMU_OFF \
869 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
870
871/* SCTLR_EL1 specific flags. */
872#ifdef CONFIG_CPU_BIG_ENDIAN
873#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
874#else
875#define ENDIAN_SET_EL1 0
876#endif
877
878#define INIT_SCTLR_EL1_MMU_OFF \
879 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
880 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
881
882#define INIT_SCTLR_EL1_MMU_ON \
883 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
884 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \
885 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \
886 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
887 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \
888 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \
889 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
890
891/* MAIR_ELx memory attributes (used by Linux) */
892#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
893#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
894#define MAIR_ATTR_NORMAL_NC UL(0x44)
895#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
896#define MAIR_ATTR_NORMAL UL(0xff)
897#define MAIR_ATTR_MASK UL(0xff)
898
899/* Position the attr at the correct index */
900#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
901
902/* id_aa64mmfr0 */
903#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
904#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
905#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
906#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
907#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
908#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
909#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
910#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
911
912#define ARM64_MIN_PARANGE_BITS 32
913
914#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
915#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
916#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
917#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
918#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
919
920#ifdef CONFIG_ARM64_PA_BITS_52
921#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
922#else
923#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
924#endif
925
926#if defined(CONFIG_ARM64_4K_PAGES)
927#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
928#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
929#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
930#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
931#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
932#elif defined(CONFIG_ARM64_16K_PAGES)
933#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
934#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
935#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
936#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
937#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
938#elif defined(CONFIG_ARM64_64K_PAGES)
939#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT
940#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
941#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
942#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
943#endif
944
945#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
946#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
947
948#define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
949#define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
950
951#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
952#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
953
954/* GCR_EL1 Definitions */
955#define SYS_GCR_EL1_RRND (BIT(16))
956#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
957
958#ifdef CONFIG_KASAN_HW_TAGS
959/*
960 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
961 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
962 */
963#define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
964#define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
965#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
966#define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
967#else
968#define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
969#endif
970
971#define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
972
973/* RGSR_EL1 Definitions */
974#define SYS_RGSR_EL1_TAG_MASK 0xfUL
975#define SYS_RGSR_EL1_SEED_SHIFT 8
976#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
977
978/* TFSR{,E0}_EL1 bit definitions */
979#define SYS_TFSR_EL1_TF0_SHIFT 0
980#define SYS_TFSR_EL1_TF1_SHIFT 1
981#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
982#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
983
984/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
985#define SYS_MPIDR_SAFE_VAL (BIT(31))
986
987/* GIC Hypervisor interface registers */
988/* ICH_MISR_EL2 bit definitions */
989#define ICH_MISR_EOI (1 << 0)
990#define ICH_MISR_U (1 << 1)
991
992/* ICH_LR*_EL2 bit definitions */
993#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
994
995#define ICH_LR_EOI (1ULL << 41)
996#define ICH_LR_GROUP (1ULL << 60)
997#define ICH_LR_HW (1ULL << 61)
998#define ICH_LR_STATE (3ULL << 62)
999#define ICH_LR_PENDING_BIT (1ULL << 62)
1000#define ICH_LR_ACTIVE_BIT (1ULL << 63)
1001#define ICH_LR_PHYS_ID_SHIFT 32
1002#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
1003#define ICH_LR_PRIORITY_SHIFT 48
1004#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
1005
1006/* ICH_HCR_EL2 bit definitions */
1007#define ICH_HCR_EN (1 << 0)
1008#define ICH_HCR_UIE (1 << 1)
1009#define ICH_HCR_NPIE (1 << 3)
1010#define ICH_HCR_TC (1 << 10)
1011#define ICH_HCR_TALL0 (1 << 11)
1012#define ICH_HCR_TALL1 (1 << 12)
1013#define ICH_HCR_TDIR (1 << 14)
1014#define ICH_HCR_EOIcount_SHIFT 27
1015#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
1016
1017/* ICH_VMCR_EL2 bit definitions */
1018#define ICH_VMCR_ACK_CTL_SHIFT 2
1019#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
1020#define ICH_VMCR_FIQ_EN_SHIFT 3
1021#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
1022#define ICH_VMCR_CBPR_SHIFT 4
1023#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
1024#define ICH_VMCR_EOIM_SHIFT 9
1025#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
1026#define ICH_VMCR_BPR1_SHIFT 18
1027#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1028#define ICH_VMCR_BPR0_SHIFT 21
1029#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1030#define ICH_VMCR_PMR_SHIFT 24
1031#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
1032#define ICH_VMCR_ENG0_SHIFT 0
1033#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
1034#define ICH_VMCR_ENG1_SHIFT 1
1035#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
1036
1037/* ICH_VTR_EL2 bit definitions */
1038#define ICH_VTR_PRI_BITS_SHIFT 29
1039#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1040#define ICH_VTR_ID_BITS_SHIFT 23
1041#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1042#define ICH_VTR_SEIS_SHIFT 22
1043#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
1044#define ICH_VTR_A3V_SHIFT 21
1045#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1046#define ICH_VTR_TDS_SHIFT 19
1047#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
1048
1049/*
1050 * Permission Indirection Extension (PIE) permission encodings.
1051 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
1052 */
1053#define PIE_NONE_O UL(0x0)
1054#define PIE_R_O UL(0x1)
1055#define PIE_X_O UL(0x2)
1056#define PIE_RX_O UL(0x3)
1057#define PIE_RW_O UL(0x5)
1058#define PIE_RWnX_O UL(0x6)
1059#define PIE_RWX_O UL(0x7)
1060#define PIE_R UL(0x8)
1061#define PIE_GCS UL(0x9)
1062#define PIE_RX UL(0xa)
1063#define PIE_RW UL(0xc)
1064#define PIE_RWX UL(0xe)
1065
1066#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
1067
1068/*
1069 * Permission Overlay Extension (POE) permission encodings.
1070 */
1071#define POE_NONE UL(0x0)
1072#define POE_R UL(0x1)
1073#define POE_X UL(0x2)
1074#define POE_RX UL(0x3)
1075#define POE_W UL(0x4)
1076#define POE_RW UL(0x5)
1077#define POE_XW UL(0x6)
1078#define POE_RXW UL(0x7)
1079#define POE_MASK UL(0xf)
1080
1081/* Initial value for Permission Overlay Extension for EL0 */
1082#define POR_EL0_INIT POE_RXW
1083
1084/*
1085 * Definitions for Guarded Control Stack
1086 */
1087
1088#define GCS_CAP_ADDR_MASK GENMASK(63, 12)
1089#define GCS_CAP_ADDR_SHIFT 12
1090#define GCS_CAP_ADDR_WIDTH 52
1091#define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x)
1092
1093#define GCS_CAP_TOKEN_MASK GENMASK(11, 0)
1094#define GCS_CAP_TOKEN_SHIFT 0
1095#define GCS_CAP_TOKEN_WIDTH 12
1096#define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x)
1097
1098#define GCS_CAP_VALID_TOKEN 0x1
1099#define GCS_CAP_IN_PROGRESS_TOKEN 0x5
1100
1101#define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
1102 GCS_CAP_VALID_TOKEN)
1103
1104#define ARM64_FEATURE_FIELD_BITS 4
1105
1106/* Defined for compatibility only, do not add new users. */
1107#define ARM64_FEATURE_MASK(x) (x##_MASK)
1108
1109#ifdef __ASSEMBLY__
1110
1111 .macro mrs_s, rt, sreg
1112 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1113 .endm
1114
1115 .macro msr_s, sreg, rt
1116 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1117 .endm
1118
1119#else
1120
1121#include <linux/bitfield.h>
1122#include <linux/build_bug.h>
1123#include <linux/types.h>
1124#include <asm/alternative.h>
1125
1126#define DEFINE_MRS_S \
1127 __DEFINE_ASM_GPR_NUMS \
1128" .macro mrs_s, rt, sreg\n" \
1129 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
1130" .endm\n"
1131
1132#define DEFINE_MSR_S \
1133 __DEFINE_ASM_GPR_NUMS \
1134" .macro msr_s, sreg, rt\n" \
1135 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1136" .endm\n"
1137
1138#define UNDEFINE_MRS_S \
1139" .purgem mrs_s\n"
1140
1141#define UNDEFINE_MSR_S \
1142" .purgem msr_s\n"
1143
1144#define __mrs_s(v, r) \
1145 DEFINE_MRS_S \
1146" mrs_s " v ", " __stringify(r) "\n" \
1147 UNDEFINE_MRS_S
1148
1149#define __msr_s(r, v) \
1150 DEFINE_MSR_S \
1151" msr_s " __stringify(r) ", " v "\n" \
1152 UNDEFINE_MSR_S
1153
1154/*
1155 * Unlike read_cpuid, calls to read_sysreg are never expected to be
1156 * optimized away or replaced with synthetic values.
1157 */
1158#define read_sysreg(r) ({ \
1159 u64 __val; \
1160 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1161 __val; \
1162})
1163
1164/*
1165 * The "Z" constraint normally means a zero immediate, but when combined with
1166 * the "%x0" template means XZR.
1167 */
1168#define write_sysreg(v, r) do { \
1169 u64 __val = (u64)(v); \
1170 asm volatile("msr " __stringify(r) ", %x0" \
1171 : : "rZ" (__val)); \
1172} while (0)
1173
1174/*
1175 * For registers without architectural names, or simply unsupported by
1176 * GAS.
1177 *
1178 * __check_r forces warnings to be generated by the compiler when
1179 * evaluating r which wouldn't normally happen due to being passed to
1180 * the assembler via __stringify(r).
1181 */
1182#define read_sysreg_s(r) ({ \
1183 u64 __val; \
1184 u32 __maybe_unused __check_r = (u32)(r); \
1185 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1186 __val; \
1187})
1188
1189#define write_sysreg_s(v, r) do { \
1190 u64 __val = (u64)(v); \
1191 u32 __maybe_unused __check_r = (u32)(r); \
1192 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
1193} while (0)
1194
1195/*
1196 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1197 * set mask are set. Other bits are left as-is.
1198 */
1199#define sysreg_clear_set(sysreg, clear, set) do { \
1200 u64 __scs_val = read_sysreg(sysreg); \
1201 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1202 if (__scs_new != __scs_val) \
1203 write_sysreg(__scs_new, sysreg); \
1204} while (0)
1205
1206#define sysreg_clear_set_s(sysreg, clear, set) do { \
1207 u64 __scs_val = read_sysreg_s(sysreg); \
1208 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1209 if (__scs_new != __scs_val) \
1210 write_sysreg_s(__scs_new, sysreg); \
1211} while (0)
1212
1213#define read_sysreg_par() ({ \
1214 u64 par; \
1215 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1216 par = read_sysreg(par_el1); \
1217 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1218 par; \
1219})
1220
1221#define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val
1222
1223#define SYS_FIELD_GET(reg, field, val) \
1224 FIELD_GET(reg##_##field##_MASK, val)
1225
1226#define SYS_FIELD_PREP(reg, field, val) \
1227 FIELD_PREP(reg##_##field##_MASK, val)
1228
1229#define SYS_FIELD_PREP_ENUM(reg, field, val) \
1230 FIELD_PREP(reg##_##field##_MASK, \
1231 SYS_FIELD_VALUE(reg, field, val))
1232
1233#endif
1234
1235#endif /* __ASM_SYSREG_H */