tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
3
4#include <linux/bitfield.h>
5#include <linux/bitops.h>
6#include <linux/device.h>
7#include <linux/err.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/spinlock.h>
14#include <linux/types.h>
15
16/*
17 * There are 2 YU GPIO blocks:
18 * gpio[0]: HOST_GPIO0->HOST_GPIO31
19 * gpio[1]: HOST_GPIO32->HOST_GPIO55
20 */
21#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
22#define MLXBF3_GPIO_MAX_PINS_BLOCK0 32
23#define MLXBF3_GPIO_MAX_PINS_BLOCK1 24
24
25/*
26 * fw_gpio[x] block registers and their offset
27 */
28#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00
29#define MLXBF_GPIO_FW_DATA_OUT_SET 0x04
30
31#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00
32#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04
33
34#define MLXBF_GPIO_CAUSE_RISE_EN 0x00
35#define MLXBF_GPIO_CAUSE_FALL_EN 0x04
36#define MLXBF_GPIO_READ_DATA_IN 0x08
37
38#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00
39#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14
40#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18
41
42#define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0)
43
44struct mlxbf3_gpio_context {
45 struct gpio_chip gc;
46
47 /* YU GPIO block address */
48 void __iomem *gpio_set_io;
49 void __iomem *gpio_clr_io;
50 void __iomem *gpio_io;
51
52 /* YU GPIO cause block address */
53 void __iomem *gpio_cause_io;
54};
55
56static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
57{
58 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
59 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
60 irq_hw_number_t offset = irqd_to_hwirq(irqd);
61 unsigned long flags;
62 u32 val;
63
64 gpiochip_enable_irq(gc, offset);
65
66 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
67 writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
68
69 val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
70 val |= BIT(offset);
71 writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
72 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
73}
74
75static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
76{
77 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
78 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
79 irq_hw_number_t offset = irqd_to_hwirq(irqd);
80 unsigned long flags;
81 u32 val;
82
83 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
84 val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
85 val &= ~BIT(offset);
86 writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
87
88 writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
89 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
90
91 gpiochip_disable_irq(gc, offset);
92}
93
94static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
95{
96 struct mlxbf3_gpio_context *gs = ptr;
97 struct gpio_chip *gc = &gs->gc;
98 unsigned long pending;
99 u32 level;
100
101 pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0);
102 writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
103
104 for_each_set_bit(level, &pending, gc->ngpio)
105 generic_handle_domain_irq(gc->irq.domain, level);
106
107 return IRQ_RETVAL(pending);
108}
109
110static int
111mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
112{
113 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
114 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
115 irq_hw_number_t offset = irqd_to_hwirq(irqd);
116 unsigned long flags;
117 u32 val;
118
119 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
120
121 switch (type & IRQ_TYPE_SENSE_MASK) {
122 case IRQ_TYPE_EDGE_BOTH:
123 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
124 val |= BIT(offset);
125 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
126 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
127 val |= BIT(offset);
128 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
129 break;
130 case IRQ_TYPE_EDGE_RISING:
131 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
132 val |= BIT(offset);
133 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
134 break;
135 case IRQ_TYPE_EDGE_FALLING:
136 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
137 val |= BIT(offset);
138 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
139 break;
140 default:
141 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
142 return -EINVAL;
143 }
144
145 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
146
147 irq_set_handler_locked(irqd, handle_edge_irq);
148
149 return 0;
150}
151
152/* This function needs to be defined for handle_edge_irq() */
153static void mlxbf3_gpio_irq_ack(struct irq_data *data)
154{
155}
156
157static const struct irq_chip gpio_mlxbf3_irqchip = {
158 .name = "MLNXBF33",
159 .irq_ack = mlxbf3_gpio_irq_ack,
160 .irq_set_type = mlxbf3_gpio_irq_set_type,
161 .irq_enable = mlxbf3_gpio_irq_enable,
162 .irq_disable = mlxbf3_gpio_irq_disable,
163 .flags = IRQCHIP_IMMUTABLE,
164 GPIOCHIP_IRQ_RESOURCE_HELPERS,
165};
166
167static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip)
168{
169 unsigned int id;
170
171 switch(chip->ngpio) {
172 case MLXBF3_GPIO_MAX_PINS_BLOCK0:
173 id = 0;
174 break;
175 case MLXBF3_GPIO_MAX_PINS_BLOCK1:
176 id = 1;
177 break;
178 default:
179 return -EINVAL;
180 }
181
182 return gpiochip_add_pin_range(chip, "MLNXBF34:00",
183 chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK,
184 chip->ngpio);
185}
186
187static int mlxbf3_gpio_probe(struct platform_device *pdev)
188{
189 struct device *dev = &pdev->dev;
190 struct mlxbf3_gpio_context *gs;
191 struct gpio_irq_chip *girq;
192 struct gpio_chip *gc;
193 int ret, irq;
194
195 gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
196 if (!gs)
197 return -ENOMEM;
198
199 gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
200 if (IS_ERR(gs->gpio_io))
201 return PTR_ERR(gs->gpio_io);
202
203 gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1);
204 if (IS_ERR(gs->gpio_cause_io))
205 return PTR_ERR(gs->gpio_cause_io);
206
207 gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2);
208 if (IS_ERR(gs->gpio_set_io))
209 return PTR_ERR(gs->gpio_set_io);
210
211 gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
212 if (IS_ERR(gs->gpio_clr_io))
213 return PTR_ERR(gs->gpio_clr_io);
214 gc = &gs->gc;
215
216 ret = bgpio_init(gc, dev, 4,
217 gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
218 gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
219 gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
220 gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
221 gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);
222 if (ret)
223 return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__);
224
225 gc->request = gpiochip_generic_request;
226 gc->free = gpiochip_generic_free;
227 gc->owner = THIS_MODULE;
228 gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges;
229
230 irq = platform_get_irq(pdev, 0);
231 if (irq >= 0) {
232 girq = &gs->gc.irq;
233 gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
234 girq->default_type = IRQ_TYPE_NONE;
235 /* This will let us handle the parent IRQ in the driver */
236 girq->num_parents = 0;
237 girq->parents = NULL;
238 girq->parent_handler = NULL;
239 girq->handler = handle_bad_irq;
240
241 /*
242 * Directly request the irq here instead of passing
243 * a flow-handler because the irq is shared.
244 */
245 ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler,
246 IRQF_SHARED, dev_name(dev), gs);
247 if (ret)
248 return dev_err_probe(dev, ret, "failed to request IRQ");
249 }
250
251 platform_set_drvdata(pdev, gs);
252
253 ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
254 if (ret)
255 dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
256
257 return 0;
258}
259
260static void mlxbf3_gpio_shutdown(struct platform_device *pdev)
261{
262 struct mlxbf3_gpio_context *gs = platform_get_drvdata(pdev);
263
264 /* Disable and clear all interrupts */
265 writel(0, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
266 writel(MLXBF_GPIO_CLR_ALL_INTS, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
267}
268
269static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = {
270 { "MLNXBF33", 0 },
271 {}
272};
273MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);
274
275static struct platform_driver mlxbf3_gpio_driver = {
276 .driver = {
277 .name = "mlxbf3_gpio",
278 .acpi_match_table = mlxbf3_gpio_acpi_match,
279 },
280 .probe = mlxbf3_gpio_probe,
281 .shutdown = mlxbf3_gpio_shutdown,
282};
283module_platform_driver(mlxbf3_gpio_driver);
284
285MODULE_SOFTDEP("pre: pinctrl-mlxbf3");
286MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
287MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
288MODULE_LICENSE("Dual BSD/GPL");