tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Nuvoton NPCM845 Pin Controller and GPIO
8
9maintainers:
10 - Tomer Maimon <tmaimon77@gmail.com>
11
12description:
13 The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
14 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
15 and multiple functions that directly connect the pin to different
16 hardware blocks.
17
18properties:
19 compatible:
20 const: nuvoton,npcm845-pinctrl
21
22 ranges:
23 maxItems: 1
24
25 '#address-cells':
26 const: 1
27
28 '#size-cells':
29 const: 1
30
31 nuvoton,sysgcr:
32 $ref: /schemas/types.yaml#/definitions/phandle
33 description: a phandle to access GCR registers.
34
35patternProperties:
36 '^gpio@':
37 type: object
38 additionalProperties: false
39
40 description:
41 Eight GPIO banks that each contain 32 GPIOs.
42
43 properties:
44 gpio-controller: true
45
46 '#gpio-cells':
47 const: 2
48
49 reg:
50 maxItems: 1
51
52 interrupts:
53 maxItems: 1
54
55 gpio-ranges:
56 maxItems: 1
57
58 required:
59 - gpio-controller
60 - '#gpio-cells'
61 - reg
62 - interrupts
63 - gpio-ranges
64
65 '-mux$':
66 $ref: pinmux-node.yaml#
67
68 properties:
69 groups:
70 description:
71 One or more groups of pins to mux to a certain function
72 items:
73 enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
74 smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
75 smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
76 smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
77 spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
78 smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
79 bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
80 fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
81 fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
82 fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
83 r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
84 i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
85 smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
86 pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
87 mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
88 smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
89 spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
90 smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
91 spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
92 hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
93
94 function:
95 description:
96 The function that a group of pins is muxed to
97 enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
98 smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
99 smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
100 smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
101 spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
102 uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
103 r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
104 fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
105 fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
106 pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
107 ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
108 smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
109 sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
110 mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
111 smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
112 faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
113 smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
114 smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
115 hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
116 bu6, gpo187 ]
117
118 dependencies:
119 groups: [ function ]
120 function: [ groups ]
121
122 additionalProperties: false
123
124 '^pin':
125 $ref: pincfg-node.yaml#
126
127 properties:
128 pins:
129 description:
130 A list of pins to configure in certain ways, such as enabling
131 debouncing
132 items:
133 pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])'
134
135 bias-disable: true
136
137 bias-pull-up: true
138
139 bias-pull-down: true
140
141 input-enable: true
142
143 output-low: true
144
145 output-high: true
146
147 drive-push-pull: true
148
149 drive-open-drain: true
150
151 input-debounce:
152 description:
153 Debouncing periods in microseconds, one period per interrupt
154 bank found in the controller
155 minItems: 1
156 maxItems: 4
157
158 slew-rate:
159 description: |
160 0: Low rate
161 1: High rate
162 enum: [0, 1]
163
164 drive-strength:
165 enum: [ 0, 1, 2, 4, 8, 12 ]
166
167 additionalProperties: false
168
169allOf:
170 - $ref: pinctrl.yaml#
171
172required:
173 - compatible
174 - ranges
175 - '#address-cells'
176 - '#size-cells'
177 - nuvoton,sysgcr
178
179additionalProperties: false
180
181examples:
182 - |
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 #include <dt-bindings/gpio/gpio.h>
185
186 soc {
187 #address-cells = <2>;
188 #size-cells = <2>;
189
190 pinctrl: pinctrl@f0010000 {
191 compatible = "nuvoton,npcm845-pinctrl";
192 ranges = <0x0 0x0 0xf0010000 0x8000>;
193 #address-cells = <1>;
194 #size-cells = <1>;
195 nuvoton,sysgcr = <&gcr>;
196
197 gpio0: gpio@0 {
198 gpio-controller;
199 #gpio-cells = <2>;
200 reg = <0x0 0xb0>;
201 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
202 gpio-ranges = <&pinctrl 0 0 32>;
203 };
204
205 fanin0_pin: fanin0-mux {
206 groups = "fanin0";
207 function = "fanin0";
208 };
209
210 pin34_slew: pin34-slew {
211 pins = "GPIO34/I3C4_SDA";
212 bias-disable;
213 };
214 };
215 };