tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26#include "amdgpu_ras.h"
27
28/* max number of IP instances */
29#define AMDGPU_MAX_SDMA_INSTANCES 16
30
31enum amdgpu_sdma_irq {
32 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
33 AMDGPU_SDMA_IRQ_INSTANCE1,
34 AMDGPU_SDMA_IRQ_INSTANCE2,
35 AMDGPU_SDMA_IRQ_INSTANCE3,
36 AMDGPU_SDMA_IRQ_INSTANCE4,
37 AMDGPU_SDMA_IRQ_INSTANCE5,
38 AMDGPU_SDMA_IRQ_INSTANCE6,
39 AMDGPU_SDMA_IRQ_INSTANCE7,
40 AMDGPU_SDMA_IRQ_INSTANCE8,
41 AMDGPU_SDMA_IRQ_INSTANCE9,
42 AMDGPU_SDMA_IRQ_INSTANCE10,
43 AMDGPU_SDMA_IRQ_INSTANCE11,
44 AMDGPU_SDMA_IRQ_INSTANCE12,
45 AMDGPU_SDMA_IRQ_INSTANCE13,
46 AMDGPU_SDMA_IRQ_INSTANCE14,
47 AMDGPU_SDMA_IRQ_INSTANCE15,
48 AMDGPU_SDMA_IRQ_LAST
49};
50
51#define NUM_SDMA(x) hweight32(x)
52
53struct amdgpu_sdma_instance {
54 /* SDMA firmware */
55 const struct firmware *fw;
56 uint32_t fw_version;
57 uint32_t feature_version;
58
59 struct amdgpu_ring ring;
60 struct amdgpu_ring page;
61 bool burst_nop;
62 uint32_t aid_id;
63
64 struct amdgpu_bo *sdma_fw_obj;
65 uint64_t sdma_fw_gpu_addr;
66 uint32_t *sdma_fw_ptr;
67};
68
69enum amdgpu_sdma_ras_memory_id {
70 AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
71 AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
72 AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
73 AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
74 AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
75 AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
76 AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
77 AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
78 AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
79 AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
80 AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
81 AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
82 AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
83 AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
84 AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
85 AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
86 AMDGPU_SDMA_UCODE_BUF = 17,
87 AMDGPU_SDMA_RB_CMD_BUF = 18,
88 AMDGPU_SDMA_IB_CMD_BUF = 19,
89 AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
90 AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
91 AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
92 AMDGPU_SDMA_DATA_LUT_FIFO = 23,
93 AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
94 AMDGPU_SDMA_MEMORY_BLOCK_LAST,
95};
96
97struct amdgpu_sdma_ras {
98 struct amdgpu_ras_block_object ras_block;
99};
100
101struct amdgpu_sdma {
102 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
103 struct amdgpu_irq_src trap_irq;
104 struct amdgpu_irq_src illegal_inst_irq;
105 struct amdgpu_irq_src ecc_irq;
106 struct amdgpu_irq_src vm_hole_irq;
107 struct amdgpu_irq_src doorbell_invalid_irq;
108 struct amdgpu_irq_src pool_timeout_irq;
109 struct amdgpu_irq_src srbm_write_irq;
110 struct amdgpu_irq_src ctxt_empty_irq;
111
112 int num_instances;
113 uint32_t sdma_mask;
114 int num_inst_per_aid;
115 uint32_t srbm_soft_reset;
116 bool has_page_queue;
117 struct ras_common_if *ras_if;
118 struct amdgpu_sdma_ras *ras;
119 uint32_t *ip_dump;
120 uint32_t supported_reset;
121};
122
123/*
124 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
125 * But currently, we use sdma to move data.
126 */
127struct amdgpu_buffer_funcs {
128 /* maximum bytes in a single operation */
129 uint32_t copy_max_bytes;
130
131 /* number of dw to reserve per operation */
132 unsigned copy_num_dw;
133
134 /* used for buffer migration */
135 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
136 /* src addr in bytes */
137 uint64_t src_offset,
138 /* dst addr in bytes */
139 uint64_t dst_offset,
140 /* number of byte to transfer */
141 uint32_t byte_count,
142 uint32_t copy_flags);
143
144 /* maximum bytes in a single operation */
145 uint32_t fill_max_bytes;
146
147 /* number of dw to reserve per operation */
148 unsigned fill_num_dw;
149
150 /* used for buffer clearing */
151 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
152 /* value to write to memory */
153 uint32_t src_data,
154 /* dst addr in bytes */
155 uint64_t dst_offset,
156 /* number of byte to fill */
157 uint32_t byte_count);
158};
159
160#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
161#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
162
163struct amdgpu_sdma_instance *
164amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
165int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
166uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
167int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
168 struct ras_common_if *ras_block);
169int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
170 void *err_data,
171 struct amdgpu_iv_entry *entry);
172int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
173 struct amdgpu_irq_src *source,
174 struct amdgpu_iv_entry *entry);
175int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
176 bool duplicate);
177void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
178 bool duplicate);
179int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
180void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev);
181int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev);
182void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev);
183#endif