tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,sa8775p-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x4-pcie-phy
22 - qcom,sar2130p-qmp-gen3x2-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
25 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
26 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
27 - qcom,sdm845-qhp-pcie-phy
28 - qcom,sdm845-qmp-pcie-phy
29 - qcom,sdx55-qmp-pcie-phy
30 - qcom,sdx65-qmp-gen4x2-pcie-phy
31 - qcom,sm8150-qmp-gen3x1-pcie-phy
32 - qcom,sm8150-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-gen3x1-pcie-phy
34 - qcom,sm8250-qmp-gen3x2-pcie-phy
35 - qcom,sm8250-qmp-modem-pcie-phy
36 - qcom,sm8350-qmp-gen3x1-pcie-phy
37 - qcom,sm8350-qmp-gen3x2-pcie-phy
38 - qcom,sm8450-qmp-gen3x1-pcie-phy
39 - qcom,sm8450-qmp-gen4x2-pcie-phy
40 - qcom,sm8550-qmp-gen3x2-pcie-phy
41 - qcom,sm8550-qmp-gen4x2-pcie-phy
42 - qcom,sm8650-qmp-gen3x2-pcie-phy
43 - qcom,sm8650-qmp-gen4x2-pcie-phy
44 - qcom,x1e80100-qmp-gen3x2-pcie-phy
45 - qcom,x1e80100-qmp-gen4x2-pcie-phy
46 - qcom,x1e80100-qmp-gen4x4-pcie-phy
47 - qcom,x1e80100-qmp-gen4x8-pcie-phy
48
49 reg:
50 minItems: 1
51 maxItems: 2
52
53 clocks:
54 minItems: 5
55 maxItems: 7
56
57 clock-names:
58 minItems: 5
59 items:
60 - const: aux
61 - const: cfg_ahb
62 - const: ref
63 - enum: [rchng, refgen]
64 - const: pipe
65 - const: pipediv2
66 - const: phy_aux
67
68 power-domains:
69 maxItems: 1
70
71 resets:
72 minItems: 1
73 maxItems: 2
74
75 reset-names:
76 minItems: 1
77 items:
78 - const: phy
79 - const: phy_nocsr
80
81 vdda-phy-supply: true
82
83 vdda-pll-supply: true
84
85 vdda-qref-supply: true
86
87 qcom,4ln-config-sel:
88 description: PCIe 4-lane configuration
89 $ref: /schemas/types.yaml#/definitions/phandle-array
90 items:
91 - items:
92 - description: phandle of TCSR syscon
93 - description: offset of PCIe 4-lane configuration register
94 - description: offset of configuration bit for this PHY
95
96 "#clock-cells": true
97
98 clock-output-names:
99 maxItems: 1
100
101 "#phy-cells":
102 const: 0
103
104required:
105 - compatible
106 - reg
107 - clocks
108 - clock-names
109 - resets
110 - reset-names
111 - vdda-phy-supply
112 - vdda-pll-supply
113 - "#clock-cells"
114 - clock-output-names
115 - "#phy-cells"
116
117additionalProperties: false
118
119allOf:
120 - if:
121 properties:
122 compatible:
123 contains:
124 enum:
125 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
126 - qcom,x1e80100-qmp-gen4x4-pcie-phy
127 then:
128 properties:
129 reg:
130 items:
131 - description: port a
132 - description: port b
133 required:
134 - qcom,4ln-config-sel
135 else:
136 properties:
137 reg:
138 maxItems: 1
139
140 - if:
141 properties:
142 compatible:
143 contains:
144 enum:
145 - qcom,sar2130p-qmp-gen3x2-pcie-phy
146 - qcom,sc8180x-qmp-pcie-phy
147 - qcom,sdm845-qhp-pcie-phy
148 - qcom,sdm845-qmp-pcie-phy
149 - qcom,sdx55-qmp-pcie-phy
150 - qcom,sm8150-qmp-gen3x1-pcie-phy
151 - qcom,sm8150-qmp-gen3x2-pcie-phy
152 - qcom,sm8250-qmp-gen3x1-pcie-phy
153 - qcom,sm8250-qmp-gen3x2-pcie-phy
154 - qcom,sm8250-qmp-modem-pcie-phy
155 - qcom,sm8350-qmp-gen3x1-pcie-phy
156 - qcom,sm8350-qmp-gen3x2-pcie-phy
157 - qcom,sm8450-qmp-gen3x1-pcie-phy
158 - qcom,sm8450-qmp-gen3x2-pcie-phy
159 - qcom,sm8550-qmp-gen3x2-pcie-phy
160 - qcom,sm8550-qmp-gen4x2-pcie-phy
161 - qcom,sm8650-qmp-gen3x2-pcie-phy
162 - qcom,sm8650-qmp-gen4x2-pcie-phy
163 then:
164 properties:
165 clocks:
166 maxItems: 5
167 clock-names:
168 maxItems: 5
169
170 - if:
171 properties:
172 compatible:
173 contains:
174 enum:
175 - qcom,qcs615-qmp-gen3x1-pcie-phy
176 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
177 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
178 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
179 - qcom,x1e80100-qmp-gen3x2-pcie-phy
180 - qcom,x1e80100-qmp-gen4x2-pcie-phy
181 - qcom,x1e80100-qmp-gen4x4-pcie-phy
182 - qcom,x1e80100-qmp-gen4x8-pcie-phy
183 then:
184 properties:
185 clocks:
186 minItems: 6
187 clock-names:
188 minItems: 6
189
190 - if:
191 properties:
192 compatible:
193 contains:
194 enum:
195 - qcom,sa8775p-qmp-gen4x2-pcie-phy
196 - qcom,sa8775p-qmp-gen4x4-pcie-phy
197 then:
198 properties:
199 clocks:
200 minItems: 7
201 clock-names:
202 minItems: 7
203
204 - if:
205 properties:
206 compatible:
207 contains:
208 enum:
209 - qcom,sm8550-qmp-gen4x2-pcie-phy
210 - qcom,sm8650-qmp-gen4x2-pcie-phy
211 - qcom,x1e80100-qmp-gen4x2-pcie-phy
212 - qcom,x1e80100-qmp-gen4x4-pcie-phy
213 - qcom,x1e80100-qmp-gen4x8-pcie-phy
214 then:
215 properties:
216 resets:
217 minItems: 2
218 reset-names:
219 minItems: 2
220 else:
221 properties:
222 resets:
223 maxItems: 1
224 reset-names:
225 maxItems: 1
226
227 - if:
228 properties:
229 compatible:
230 contains:
231 enum:
232 - qcom,sm8450-qmp-gen4x2-pcie-phy
233 - qcom,sm8550-qmp-gen4x2-pcie-phy
234 - qcom,sm8650-qmp-gen4x2-pcie-phy
235 then:
236 properties:
237 "#clock-cells":
238 const: 1
239 else:
240 properties:
241 "#clock-cells":
242 const: 0
243
244examples:
245 - |
246 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
247
248 pcie2b_phy: phy@1c18000 {
249 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
250 reg = <0x01c18000 0x2000>;
251
252 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
253 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
254 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
255 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
256 <&gcc GCC_PCIE_2B_PIPE_CLK>,
257 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
258 clock-names = "aux", "cfg_ahb", "ref", "rchng",
259 "pipe", "pipediv2";
260
261 power-domains = <&gcc PCIE_2B_GDSC>;
262
263 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
264 reset-names = "phy";
265
266 vdda-phy-supply = <&vreg_l6d>;
267 vdda-pll-supply = <&vreg_l4d>;
268
269 #clock-cells = <0>;
270 clock-output-names = "pcie_2b_pipe_clk";
271
272 #phy-cells = <0>;
273 };
274
275 pcie2a_phy: phy@1c24000 {
276 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
277 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
278
279 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
280 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
281 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
282 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
283 <&gcc GCC_PCIE_2A_PIPE_CLK>,
284 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
285 clock-names = "aux", "cfg_ahb", "ref", "rchng",
286 "pipe", "pipediv2";
287
288 power-domains = <&gcc PCIE_2A_GDSC>;
289
290 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
291 reset-names = "phy";
292
293 vdda-phy-supply = <&vreg_l6d>;
294 vdda-pll-supply = <&vreg_l4d>;
295
296 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
297
298 #clock-cells = <0>;
299 clock-output-names = "pcie_2a_pipe_clk";
300
301 #phy-cells = <0>;
302 };