tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 oneOf:
19 - enum:
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq8074-qmp-gen3-pcie-phy
22 - qcom,ipq8074-qmp-pcie-phy
23 - qcom,ipq9574-qmp-gen3x1-pcie-phy
24 - qcom,ipq9574-qmp-gen3x2-pcie-phy
25 - items:
26 - enum:
27 - qcom,ipq5424-qmp-gen3x1-pcie-phy
28 - const: qcom,ipq9574-qmp-gen3x1-pcie-phy
29 - items:
30 - enum:
31 - qcom,ipq5424-qmp-gen3x2-pcie-phy
32 - const: qcom,ipq9574-qmp-gen3x2-pcie-phy
33
34 reg:
35 items:
36 - description: serdes
37
38 clocks:
39 maxItems: 3
40
41 clock-names:
42 items:
43 - const: aux
44 - const: cfg_ahb
45 - const: pipe
46
47 resets:
48 maxItems: 2
49
50 reset-names:
51 items:
52 - const: phy
53 - const: common
54
55 "#clock-cells":
56 const: 0
57
58 clock-output-names:
59 maxItems: 1
60
61 "#phy-cells":
62 const: 0
63
64required:
65 - compatible
66 - reg
67 - clocks
68 - clock-names
69 - resets
70 - reset-names
71 - "#clock-cells"
72 - clock-output-names
73 - "#phy-cells"
74
75additionalProperties: false
76
77examples:
78 - |
79 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
80 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
81
82 phy@84000 {
83 compatible = "qcom,ipq6018-qmp-pcie-phy";
84 reg = <0x00084000 0x1000>;
85
86 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
87 <&gcc GCC_PCIE0_AHB_CLK>,
88 <&gcc GCC_PCIE0_PIPE_CLK>;
89 clock-names = "aux",
90 "cfg_ahb",
91 "pipe";
92
93 clock-output-names = "gcc_pcie0_pipe_clk_src";
94 #clock-cells = <0>;
95
96 #phy-cells = <0>;
97
98 resets = <&gcc GCC_PCIE0_PHY_BCR>,
99 <&gcc GCC_PCIE0PHY_PHY_BCR>;
100 reset-names = "phy",
101 "common";
102 };