tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef _XE_ENGINE_REGS_H_
7#define _XE_ENGINE_REGS_H_
8
9#include <asm/page.h>
10
11#include "regs/xe_reg_defs.h"
12
13/*
14 * These *_BASE values represent the MMIO offset where each hardware engine's
15 * registers start. The other definitions in this header are parameterized
16 * macros that will take one of these values as a parameter.
17 */
18#define RENDER_RING_BASE 0x02000
19#define BSD_RING_BASE 0x1c0000
20#define BSD2_RING_BASE 0x1c4000
21#define BSD3_RING_BASE 0x1d0000
22#define BSD4_RING_BASE 0x1d4000
23#define XEHP_BSD5_RING_BASE 0x1e0000
24#define XEHP_BSD6_RING_BASE 0x1e4000
25#define XEHP_BSD7_RING_BASE 0x1f0000
26#define XEHP_BSD8_RING_BASE 0x1f4000
27#define VEBOX_RING_BASE 0x1c8000
28#define VEBOX2_RING_BASE 0x1d8000
29#define XEHP_VEBOX3_RING_BASE 0x1e8000
30#define XEHP_VEBOX4_RING_BASE 0x1f8000
31#define COMPUTE0_RING_BASE 0x1a000
32#define COMPUTE1_RING_BASE 0x1c000
33#define COMPUTE2_RING_BASE 0x1e000
34#define COMPUTE3_RING_BASE 0x26000
35#define BLT_RING_BASE 0x22000
36#define XEHPC_BCS1_RING_BASE 0x3e0000
37#define XEHPC_BCS2_RING_BASE 0x3e2000
38#define XEHPC_BCS3_RING_BASE 0x3e4000
39#define XEHPC_BCS4_RING_BASE 0x3e6000
40#define XEHPC_BCS5_RING_BASE 0x3e8000
41#define XEHPC_BCS6_RING_BASE 0x3ea000
42#define XEHPC_BCS7_RING_BASE 0x3ec000
43#define XEHPC_BCS8_RING_BASE 0x3ee000
44#define GSCCS_RING_BASE 0x11a000
45
46#define RING_TAIL(base) XE_REG((base) + 0x30)
47#define TAIL_ADDR REG_GENMASK(20, 3)
48
49#define RING_HEAD(base) XE_REG((base) + 0x34)
50#define HEAD_ADDR REG_GENMASK(20, 2)
51
52#define RING_START(base) XE_REG((base) + 0x38)
53
54#define RING_CTL(base) XE_REG((base) + 0x3c)
55#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
56#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
57
58#define RING_START_UDW(base) XE_REG((base) + 0x48)
59
60#define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
61#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
62#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
63#define IDLE_MSG_DISABLE REG_BIT(0)
64
65#define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54)
66#define IDLE_WAIT_TIME REG_GENMASK(19, 0)
67
68#define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
69#define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
70#define RING_IPEHR(base) XE_REG((base) + 0x68)
71#define RING_INSTDONE(base) XE_REG((base) + 0x6c)
72#define RING_ACTHD(base) XE_REG((base) + 0x74)
73#define RING_DMA_FADD(base) XE_REG((base) + 0x78)
74#define RING_HWS_PGA(base) XE_REG((base) + 0x80)
75#define RING_HWSTAM(base) XE_REG((base) + 0x98)
76#define RING_MI_MODE(base) XE_REG((base) + 0x9c)
77#define RING_NOPID(base) XE_REG((base) + 0x94)
78
79#define FF_THREAD_MODE(base) XE_REG((base) + 0xa0)
80#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
81
82#define RING_INT_SRC_RPT_PTR(base) XE_REG((base) + 0xa4)
83#define RING_IMR(base) XE_REG((base) + 0xa8)
84#define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac)
85
86#define CS_INT_VEC(base) XE_REG((base) + 0x1b8)
87
88#define RING_EIR(base) XE_REG((base) + 0xb0)
89#define RING_EMR(base) XE_REG((base) + 0xb4)
90#define RING_ESR(base) XE_REG((base) + 0xb8)
91
92#define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)
93#define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13)
94
95#define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
96/*
97 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
98 * The lsb of each can be considered a separate enabling bit for encryption.
99 * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
100 * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
101 * 15:14 == Reserved => 31:30 are set to 0.
102 */
103#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8)
104#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1)
105
106#define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
107#define GHWSP_CSB_REPORT_DIS REG_BIT(15)
108#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
109#define CS_PRIORITY_MEM_READ REG_BIT(7)
110
111#define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
112#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
113
114#define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)
115#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
116#define REPLAY_MODE_GRANULARITY REG_BIT(0)
117
118#define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
119
120#define RING_BBADDR(base) XE_REG((base) + 0x140)
121#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
122
123#define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
124#define BCS_SWCTRL_DISABLE_256B REG_BIT(2)
125
126/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
127#define BLIT_CCTL(base) XE_REG((base) + 0x204)
128#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9)
129#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1)
130
131#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
132#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
133
134#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
135#define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8)
136#define CTX_CTRL_RUN_ALONE REG_BIT(7)
137#define CTX_CTRL_INDIRECT_RING_STATE_ENABLE REG_BIT(4)
138#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
139#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
140
141#define RING_MODE(base) XE_REG((base) + 0x29c)
142#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
143#define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
144
145#define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
146
147#define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4)
148#define RING_VALID_MASK 0x00000001
149#define RING_VALID 0x00000001
150#define STOP_RING REG_BIT(8)
151
152#define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8)
153#define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc)
154
155#define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4)
156#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
157#define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28)
158#define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)
159#define RING_FORCE_TO_NONPRIV_ACCESS_RD REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 1)
160#define RING_FORCE_TO_NONPRIV_ACCESS_WR REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 2)
161#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 3)
162#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
163#define RING_FORCE_TO_NONPRIV_RANGE_MASK REG_GENMASK(1, 0)
164#define RING_FORCE_TO_NONPRIV_RANGE_1 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 0)
165#define RING_FORCE_TO_NONPRIV_RANGE_4 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 1)
166#define RING_FORCE_TO_NONPRIV_RANGE_16 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 2)
167#define RING_FORCE_TO_NONPRIV_RANGE_64 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 3)
168#define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
169 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
170 RING_FORCE_TO_NONPRIV_DENY)
171#define RING_MAX_NONPRIV_SLOTS 12
172
173#define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510)
174#define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4)
175
176#define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550)
177#define EL_CTRL_LOAD REG_BIT(0)
178
179#define CS_CHICKEN1(base) XE_REG((base) + 0x580, XE_REG_OPTION_MASKED)
180#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
181#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
182#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
183#define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0)
184#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
185#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
186
187#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
188#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
189
190#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
191#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
192#define RAMDFTUNIT_CLKGATE_DIS REG_BIT(9)
193
194#define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18)
195#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
196
197#define VDBOX_CGCTL3F1C(base) XE_REG((base) + 0x3f1c)
198#define MFXPIPE_CLKGATE_DIS REG_BIT(3)
199
200#endif