Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26#include "amdgpu_socbb.h"
27
28struct common_firmware_header {
29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
31 uint16_t header_version_major; /* header version */
32 uint16_t header_version_minor; /* header version */
33 uint16_t ip_version_major; /* IP version */
34 uint16_t ip_version_minor; /* IP version */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
39};
40
41/* version_major=1, version_minor=0 */
42struct mc_firmware_header_v1_0 {
43 struct common_firmware_header header;
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46};
47
48/* version_major=1, version_minor=0 */
49struct smc_firmware_header_v1_0 {
50 struct common_firmware_header header;
51 uint32_t ucode_start_addr;
52};
53
54/* version_major=2, version_minor=0 */
55struct smc_firmware_header_v2_0 {
56 struct smc_firmware_header_v1_0 v1_0;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
58 uint32_t ppt_size_bytes; /* soft pptable size */
59};
60
61struct smc_soft_pptable_entry {
62 uint32_t id;
63 uint32_t ppt_offset_bytes;
64 uint32_t ppt_size_bytes;
65};
66
67/* version_major=2, version_minor=1 */
68struct smc_firmware_header_v2_1 {
69 struct smc_firmware_header_v1_0 v1_0;
70 uint32_t pptable_count;
71 uint32_t pptable_entry_offset;
72};
73
74struct psp_fw_legacy_bin_desc {
75 uint32_t fw_version;
76 uint32_t offset_bytes;
77 uint32_t size_bytes;
78};
79
80/* version_major=1, version_minor=0 */
81struct psp_firmware_header_v1_0 {
82 struct common_firmware_header header;
83 struct psp_fw_legacy_bin_desc sos;
84};
85
86/* version_major=1, version_minor=1 */
87struct psp_firmware_header_v1_1 {
88 struct psp_firmware_header_v1_0 v1_0;
89 struct psp_fw_legacy_bin_desc toc;
90 struct psp_fw_legacy_bin_desc kdb;
91};
92
93/* version_major=1, version_minor=2 */
94struct psp_firmware_header_v1_2 {
95 struct psp_firmware_header_v1_0 v1_0;
96 struct psp_fw_legacy_bin_desc res;
97 struct psp_fw_legacy_bin_desc kdb;
98};
99
100/* version_major=1, version_minor=3 */
101struct psp_firmware_header_v1_3 {
102 struct psp_firmware_header_v1_1 v1_1;
103 struct psp_fw_legacy_bin_desc spl;
104 struct psp_fw_legacy_bin_desc rl;
105 struct psp_fw_legacy_bin_desc sys_drv_aux;
106 struct psp_fw_legacy_bin_desc sos_aux;
107};
108
109struct psp_fw_bin_desc {
110 uint32_t fw_type;
111 uint32_t fw_version;
112 uint32_t offset_bytes;
113 uint32_t size_bytes;
114};
115
116enum psp_fw_type {
117 PSP_FW_TYPE_UNKOWN,
118 PSP_FW_TYPE_PSP_SOS,
119 PSP_FW_TYPE_PSP_SYS_DRV,
120 PSP_FW_TYPE_PSP_KDB,
121 PSP_FW_TYPE_PSP_TOC,
122 PSP_FW_TYPE_PSP_SPL,
123 PSP_FW_TYPE_PSP_RL,
124 PSP_FW_TYPE_PSP_SOC_DRV,
125 PSP_FW_TYPE_PSP_INTF_DRV,
126 PSP_FW_TYPE_PSP_DBG_DRV,
127 PSP_FW_TYPE_PSP_RAS_DRV,
128 PSP_FW_TYPE_PSP_IPKEYMGR_DRV,
129 PSP_FW_TYPE_PSP_SPDM_DRV,
130 PSP_FW_TYPE_MAX_INDEX,
131};
132
133/* version_major=2, version_minor=0 */
134struct psp_firmware_header_v2_0 {
135 struct common_firmware_header header;
136 uint32_t psp_fw_bin_count;
137 struct psp_fw_bin_desc psp_fw_bin[];
138};
139
140/* version_major=2, version_minor=1 */
141struct psp_firmware_header_v2_1 {
142 struct common_firmware_header header;
143 uint32_t psp_fw_bin_count;
144 uint32_t psp_aux_fw_bin_index;
145 struct psp_fw_bin_desc psp_fw_bin[];
146};
147
148/* version_major=1, version_minor=0 */
149struct ta_firmware_header_v1_0 {
150 struct common_firmware_header header;
151 struct psp_fw_legacy_bin_desc xgmi;
152 struct psp_fw_legacy_bin_desc ras;
153 struct psp_fw_legacy_bin_desc hdcp;
154 struct psp_fw_legacy_bin_desc dtm;
155 struct psp_fw_legacy_bin_desc securedisplay;
156};
157
158enum ta_fw_type {
159 TA_FW_TYPE_UNKOWN,
160 TA_FW_TYPE_PSP_ASD,
161 TA_FW_TYPE_PSP_XGMI,
162 TA_FW_TYPE_PSP_RAS,
163 TA_FW_TYPE_PSP_HDCP,
164 TA_FW_TYPE_PSP_DTM,
165 TA_FW_TYPE_PSP_RAP,
166 TA_FW_TYPE_PSP_SECUREDISPLAY,
167 TA_FW_TYPE_PSP_XGMI_AUX,
168 TA_FW_TYPE_MAX_INDEX,
169};
170
171/* version_major=2, version_minor=0 */
172struct ta_firmware_header_v2_0 {
173 struct common_firmware_header header;
174 uint32_t ta_fw_bin_count;
175 struct psp_fw_bin_desc ta_fw_bin[];
176};
177
178/* version_major=1, version_minor=0 */
179struct gfx_firmware_header_v1_0 {
180 struct common_firmware_header header;
181 uint32_t ucode_feature_version;
182 uint32_t jt_offset; /* jt location */
183 uint32_t jt_size; /* size of jt */
184};
185
186/* version_major=2, version_minor=0 */
187struct gfx_firmware_header_v2_0 {
188 struct common_firmware_header header;
189 uint32_t ucode_feature_version;
190 uint32_t ucode_size_bytes;
191 uint32_t ucode_offset_bytes;
192 uint32_t data_size_bytes;
193 uint32_t data_offset_bytes;
194 uint32_t ucode_start_addr_lo;
195 uint32_t ucode_start_addr_hi;
196};
197
198/* version_major=1, version_minor=0 */
199struct mes_firmware_header_v1_0 {
200 struct common_firmware_header header;
201 uint32_t mes_ucode_version;
202 uint32_t mes_ucode_size_bytes;
203 uint32_t mes_ucode_offset_bytes;
204 uint32_t mes_ucode_data_version;
205 uint32_t mes_ucode_data_size_bytes;
206 uint32_t mes_ucode_data_offset_bytes;
207 uint32_t mes_uc_start_addr_lo;
208 uint32_t mes_uc_start_addr_hi;
209 uint32_t mes_data_start_addr_lo;
210 uint32_t mes_data_start_addr_hi;
211};
212
213/* version_major=1, version_minor=0 */
214struct rlc_firmware_header_v1_0 {
215 struct common_firmware_header header;
216 uint32_t ucode_feature_version;
217 uint32_t save_and_restore_offset;
218 uint32_t clear_state_descriptor_offset;
219 uint32_t avail_scratch_ram_locations;
220 uint32_t master_pkt_description_offset;
221};
222
223/* version_major=2, version_minor=0 */
224struct rlc_firmware_header_v2_0 {
225 struct common_firmware_header header;
226 uint32_t ucode_feature_version;
227 uint32_t jt_offset; /* jt location */
228 uint32_t jt_size; /* size of jt */
229 uint32_t save_and_restore_offset;
230 uint32_t clear_state_descriptor_offset;
231 uint32_t avail_scratch_ram_locations;
232 uint32_t reg_restore_list_size;
233 uint32_t reg_list_format_start;
234 uint32_t reg_list_format_separate_start;
235 uint32_t starting_offsets_start;
236 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
237 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
238 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
239 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
240 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
241 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
242 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
243 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
244};
245
246/* version_major=2, version_minor=1 */
247struct rlc_firmware_header_v2_1 {
248 struct rlc_firmware_header_v2_0 v2_0;
249 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
250 uint32_t save_restore_list_cntl_ucode_ver;
251 uint32_t save_restore_list_cntl_feature_ver;
252 uint32_t save_restore_list_cntl_size_bytes;
253 uint32_t save_restore_list_cntl_offset_bytes;
254 uint32_t save_restore_list_gpm_ucode_ver;
255 uint32_t save_restore_list_gpm_feature_ver;
256 uint32_t save_restore_list_gpm_size_bytes;
257 uint32_t save_restore_list_gpm_offset_bytes;
258 uint32_t save_restore_list_srm_ucode_ver;
259 uint32_t save_restore_list_srm_feature_ver;
260 uint32_t save_restore_list_srm_size_bytes;
261 uint32_t save_restore_list_srm_offset_bytes;
262};
263
264/* version_major=2, version_minor=2 */
265struct rlc_firmware_header_v2_2 {
266 struct rlc_firmware_header_v2_1 v2_1;
267 uint32_t rlc_iram_ucode_size_bytes;
268 uint32_t rlc_iram_ucode_offset_bytes;
269 uint32_t rlc_dram_ucode_size_bytes;
270 uint32_t rlc_dram_ucode_offset_bytes;
271};
272
273/* version_major=2, version_minor=3 */
274struct rlc_firmware_header_v2_3 {
275 struct rlc_firmware_header_v2_2 v2_2;
276 uint32_t rlcp_ucode_version;
277 uint32_t rlcp_ucode_feature_version;
278 uint32_t rlcp_ucode_size_bytes;
279 uint32_t rlcp_ucode_offset_bytes;
280 uint32_t rlcv_ucode_version;
281 uint32_t rlcv_ucode_feature_version;
282 uint32_t rlcv_ucode_size_bytes;
283 uint32_t rlcv_ucode_offset_bytes;
284};
285
286/* version_major=2, version_minor=4 */
287struct rlc_firmware_header_v2_4 {
288 struct rlc_firmware_header_v2_3 v2_3;
289 uint32_t global_tap_delays_ucode_size_bytes;
290 uint32_t global_tap_delays_ucode_offset_bytes;
291 uint32_t se0_tap_delays_ucode_size_bytes;
292 uint32_t se0_tap_delays_ucode_offset_bytes;
293 uint32_t se1_tap_delays_ucode_size_bytes;
294 uint32_t se1_tap_delays_ucode_offset_bytes;
295 uint32_t se2_tap_delays_ucode_size_bytes;
296 uint32_t se2_tap_delays_ucode_offset_bytes;
297 uint32_t se3_tap_delays_ucode_size_bytes;
298 uint32_t se3_tap_delays_ucode_offset_bytes;
299};
300
301/* version_major=1, version_minor=0 */
302struct sdma_firmware_header_v1_0 {
303 struct common_firmware_header header;
304 uint32_t ucode_feature_version;
305 uint32_t ucode_change_version;
306 uint32_t jt_offset; /* jt location */
307 uint32_t jt_size; /* size of jt */
308};
309
310/* version_major=1, version_minor=1 */
311struct sdma_firmware_header_v1_1 {
312 struct sdma_firmware_header_v1_0 v1_0;
313 uint32_t digest_size;
314};
315
316/* version_major=2, version_minor=0 */
317struct sdma_firmware_header_v2_0 {
318 struct common_firmware_header header;
319 uint32_t ucode_feature_version;
320 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
321 uint32_t ctx_jt_offset; /* context thread jt location */
322 uint32_t ctx_jt_size; /* context thread size of jt */
323 uint32_t ctl_ucode_offset;
324 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
325 uint32_t ctl_jt_offset; /* control thread jt location */
326 uint32_t ctl_jt_size; /* control thread size of jt */
327};
328
329/* version_major=1, version_minor=0 */
330struct vpe_firmware_header_v1_0 {
331 struct common_firmware_header header;
332 uint32_t ucode_feature_version;
333 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
334 uint32_t ctx_jt_offset; /* context thread jt location */
335 uint32_t ctx_jt_size; /* context thread size of jt */
336 uint32_t ctl_ucode_offset;
337 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
338 uint32_t ctl_jt_offset; /* control thread jt location */
339 uint32_t ctl_jt_size; /* control thread size of jt */
340};
341
342/* version_major=1, version_minor=0 */
343struct umsch_mm_firmware_header_v1_0 {
344 struct common_firmware_header header;
345 uint32_t umsch_mm_ucode_version;
346 uint32_t umsch_mm_ucode_size_bytes;
347 uint32_t umsch_mm_ucode_offset_bytes;
348 uint32_t umsch_mm_ucode_data_version;
349 uint32_t umsch_mm_ucode_data_size_bytes;
350 uint32_t umsch_mm_ucode_data_offset_bytes;
351 uint32_t umsch_mm_irq_start_addr_lo;
352 uint32_t umsch_mm_irq_start_addr_hi;
353 uint32_t umsch_mm_uc_start_addr_lo;
354 uint32_t umsch_mm_uc_start_addr_hi;
355 uint32_t umsch_mm_data_start_addr_lo;
356 uint32_t umsch_mm_data_start_addr_hi;
357};
358
359/* version_major=3, version_minor=0 */
360struct sdma_firmware_header_v3_0 {
361 struct common_firmware_header header;
362 uint32_t ucode_feature_version;
363 uint32_t ucode_offset_bytes;
364 uint32_t ucode_size_bytes;
365};
366
367/* gpu info payload */
368struct gpu_info_firmware_v1_0 {
369 uint32_t gc_num_se;
370 uint32_t gc_num_cu_per_sh;
371 uint32_t gc_num_sh_per_se;
372 uint32_t gc_num_rb_per_se;
373 uint32_t gc_num_tccs;
374 uint32_t gc_num_gprs;
375 uint32_t gc_num_max_gs_thds;
376 uint32_t gc_gs_table_depth;
377 uint32_t gc_gsprim_buff_depth;
378 uint32_t gc_parameter_cache_depth;
379 uint32_t gc_double_offchip_lds_buffer;
380 uint32_t gc_wave_size;
381 uint32_t gc_max_waves_per_simd;
382 uint32_t gc_max_scratch_slots_per_cu;
383 uint32_t gc_lds_size;
384};
385
386struct gpu_info_firmware_v1_1 {
387 struct gpu_info_firmware_v1_0 v1_0;
388 uint32_t num_sc_per_sh;
389 uint32_t num_packer_per_sc;
390};
391
392/* gpu info payload
393 * version_major=1, version_minor=1 */
394struct gpu_info_firmware_v1_2 {
395 struct gpu_info_firmware_v1_1 v1_1;
396 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
397};
398
399/* version_major=1, version_minor=0 */
400struct gpu_info_firmware_header_v1_0 {
401 struct common_firmware_header header;
402 uint16_t version_major; /* version */
403 uint16_t version_minor; /* version */
404};
405
406/* version_major=1, version_minor=0 */
407struct dmcu_firmware_header_v1_0 {
408 struct common_firmware_header header;
409 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
410 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
411};
412
413/* version_major=1, version_minor=0 */
414struct dmcub_firmware_header_v1_0 {
415 struct common_firmware_header header;
416 uint32_t inst_const_bytes; /* size of instruction region, in bytes */
417 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
418};
419
420/* version_major=1, version_minor=0 */
421struct imu_firmware_header_v1_0 {
422 struct common_firmware_header header;
423 uint32_t imu_iram_ucode_size_bytes;
424 uint32_t imu_iram_ucode_offset_bytes;
425 uint32_t imu_dram_ucode_size_bytes;
426 uint32_t imu_dram_ucode_offset_bytes;
427};
428
429/* header is fixed size */
430union amdgpu_firmware_header {
431 struct common_firmware_header common;
432 struct mc_firmware_header_v1_0 mc;
433 struct smc_firmware_header_v1_0 smc;
434 struct smc_firmware_header_v2_0 smc_v2_0;
435 struct psp_firmware_header_v1_0 psp;
436 struct psp_firmware_header_v1_1 psp_v1_1;
437 struct psp_firmware_header_v1_3 psp_v1_3;
438 struct psp_firmware_header_v2_0 psp_v2_0;
439 struct psp_firmware_header_v2_0 psp_v2_1;
440 struct ta_firmware_header_v1_0 ta;
441 struct ta_firmware_header_v2_0 ta_v2_0;
442 struct gfx_firmware_header_v1_0 gfx;
443 struct gfx_firmware_header_v2_0 gfx_v2_0;
444 struct rlc_firmware_header_v1_0 rlc;
445 struct rlc_firmware_header_v2_0 rlc_v2_0;
446 struct rlc_firmware_header_v2_1 rlc_v2_1;
447 struct rlc_firmware_header_v2_2 rlc_v2_2;
448 struct rlc_firmware_header_v2_3 rlc_v2_3;
449 struct rlc_firmware_header_v2_4 rlc_v2_4;
450 struct sdma_firmware_header_v1_0 sdma;
451 struct sdma_firmware_header_v1_1 sdma_v1_1;
452 struct sdma_firmware_header_v2_0 sdma_v2_0;
453 struct sdma_firmware_header_v3_0 sdma_v3_0;
454 struct gpu_info_firmware_header_v1_0 gpu_info;
455 struct dmcu_firmware_header_v1_0 dmcu;
456 struct dmcub_firmware_header_v1_0 dmcub;
457 struct imu_firmware_header_v1_0 imu;
458 uint8_t raw[0x100];
459};
460
461#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2)
462
463/*
464 * fw loading support
465 */
466enum AMDGPU_UCODE_ID {
467 AMDGPU_UCODE_ID_CAP = 0,
468 AMDGPU_UCODE_ID_SDMA0,
469 AMDGPU_UCODE_ID_SDMA1,
470 AMDGPU_UCODE_ID_SDMA2,
471 AMDGPU_UCODE_ID_SDMA3,
472 AMDGPU_UCODE_ID_SDMA4,
473 AMDGPU_UCODE_ID_SDMA5,
474 AMDGPU_UCODE_ID_SDMA6,
475 AMDGPU_UCODE_ID_SDMA7,
476 AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
477 AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
478 AMDGPU_UCODE_ID_SDMA_RS64,
479 AMDGPU_UCODE_ID_CP_CE,
480 AMDGPU_UCODE_ID_CP_PFP,
481 AMDGPU_UCODE_ID_CP_ME,
482 AMDGPU_UCODE_ID_CP_RS64_PFP,
483 AMDGPU_UCODE_ID_CP_RS64_ME,
484 AMDGPU_UCODE_ID_CP_RS64_MEC,
485 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
486 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
487 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
488 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
489 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
490 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
491 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
492 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
493 AMDGPU_UCODE_ID_CP_MEC1,
494 AMDGPU_UCODE_ID_CP_MEC1_JT,
495 AMDGPU_UCODE_ID_CP_MEC2,
496 AMDGPU_UCODE_ID_CP_MEC2_JT,
497 AMDGPU_UCODE_ID_CP_MES,
498 AMDGPU_UCODE_ID_CP_MES_DATA,
499 AMDGPU_UCODE_ID_CP_MES1,
500 AMDGPU_UCODE_ID_CP_MES1_DATA,
501 AMDGPU_UCODE_ID_IMU_I,
502 AMDGPU_UCODE_ID_IMU_D,
503 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
504 AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
505 AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
506 AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
507 AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
508 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
509 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
510 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
511 AMDGPU_UCODE_ID_RLC_IRAM,
512 AMDGPU_UCODE_ID_RLC_DRAM,
513 AMDGPU_UCODE_ID_RLC_P,
514 AMDGPU_UCODE_ID_RLC_V,
515 AMDGPU_UCODE_ID_RLC_G,
516 AMDGPU_UCODE_ID_STORAGE,
517 AMDGPU_UCODE_ID_SMC,
518 AMDGPU_UCODE_ID_PPTABLE,
519 AMDGPU_UCODE_ID_UVD,
520 AMDGPU_UCODE_ID_UVD1,
521 AMDGPU_UCODE_ID_VCE,
522 AMDGPU_UCODE_ID_VCN,
523 AMDGPU_UCODE_ID_VCN1,
524 AMDGPU_UCODE_ID_DMCU_ERAM,
525 AMDGPU_UCODE_ID_DMCU_INTV,
526 AMDGPU_UCODE_ID_VCN0_RAM,
527 AMDGPU_UCODE_ID_VCN1_RAM,
528 AMDGPU_UCODE_ID_DMCUB,
529 AMDGPU_UCODE_ID_VPE_CTX,
530 AMDGPU_UCODE_ID_VPE_CTL,
531 AMDGPU_UCODE_ID_VPE,
532 AMDGPU_UCODE_ID_UMSCH_MM_UCODE,
533 AMDGPU_UCODE_ID_UMSCH_MM_DATA,
534 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
535 AMDGPU_UCODE_ID_P2S_TABLE,
536 AMDGPU_UCODE_ID_JPEG_RAM,
537 AMDGPU_UCODE_ID_ISP,
538 AMDGPU_UCODE_ID_MAXIMUM,
539};
540
541/* engine firmware status */
542enum AMDGPU_UCODE_STATUS {
543 AMDGPU_UCODE_STATUS_INVALID,
544 AMDGPU_UCODE_STATUS_NOT_LOADED,
545 AMDGPU_UCODE_STATUS_LOADED,
546};
547
548enum amdgpu_firmware_load_type {
549 AMDGPU_FW_LOAD_DIRECT = 0,
550 AMDGPU_FW_LOAD_PSP,
551 AMDGPU_FW_LOAD_SMU,
552 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
553};
554
555enum amdgpu_ucode_required {
556 AMDGPU_UCODE_OPTIONAL,
557 AMDGPU_UCODE_REQUIRED,
558};
559
560/* conform to smu_ucode_xfer_cz.h */
561#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
562#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
563#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
564#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
565#define AMDGPU_CPME_UCODE_LOADED 0x00000010
566#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
567#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
568#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
569
570/* amdgpu firmware info */
571struct amdgpu_firmware_info {
572 /* ucode ID */
573 enum AMDGPU_UCODE_ID ucode_id;
574 /* request_firmware */
575 const struct firmware *fw;
576 /* starting mc address */
577 uint64_t mc_addr;
578 /* kernel linear address */
579 void *kaddr;
580 /* ucode_size_bytes */
581 uint32_t ucode_size;
582 /* starting tmr mc address */
583 uint32_t tmr_mc_addr_lo;
584 uint32_t tmr_mc_addr_hi;
585};
586
587struct amdgpu_firmware {
588 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
589 enum amdgpu_firmware_load_type load_type;
590 struct amdgpu_bo *fw_buf;
591 unsigned int fw_size;
592 unsigned int max_ucodes;
593 /* firmwares are loaded by psp instead of smu from vega10 */
594 const struct amdgpu_psp_funcs *funcs;
595 struct amdgpu_bo *rbuf;
596 struct mutex mutex;
597
598 /* gpu info firmware data pointer */
599 const struct firmware *gpu_info_fw;
600
601 void *fw_buf_ptr;
602 uint64_t fw_buf_mc;
603};
604
605void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
606void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
607void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
608void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
609void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
610void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
611void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
612void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
613__printf(4, 5)
614int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
615 enum amdgpu_ucode_required required, const char *fmt, ...);
616void amdgpu_ucode_release(const struct firmware **fw);
617bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
618 uint16_t hdr_major, uint16_t hdr_minor);
619
620int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
621int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
622int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
623void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
624void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
625
626enum amdgpu_firmware_load_type
627amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
628
629const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
630
631void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
632
633#endif