tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. QCS8300 TLMM block
8
9maintainers:
10 - Jingyi Wang <quic_jingyw@quicinc.com>
11
12description: |
13 Top Level Mode Multiplexer pin controller in Qualcomm QCS8300 SoC.
14
15allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19 compatible:
20 const: qcom,qcs8300-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 gpio-reserved-ranges:
29 minItems: 1
30 maxItems: 67
31
32 gpio-line-names:
33 maxItems: 133
34
35patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-qcs8300-tlmm-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-qcs8300-tlmm-state"
42 additionalProperties: false
43
44$defs:
45 qcom-qcs8300-tlmm-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 oneOf:
60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
61 - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
62 minItems: 1
63 maxItems: 36
64
65 function:
66 description:
67 Specify the alternative function to be configured for the specified
68 pins.
69
70 enum: [ aoss_cti, atest_char, atest_usb2, audio_ref, cam_mclk,
71 cci_async, cci_i2c_scl, cci_i2c_sda, cci_timer, cri_trng,
72 dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,
73 edp0_hot, edp0_lcd, edp1_lcd, egpio, emac0_mcg0, emac0_mcg1,
74 emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux,
75 emac0_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5,
76 gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, jitter_bist,
77 mdp0_vsync0, mdp0_vsync1, mdp0_vsync3, mdp0_vsync6, mdp0_vsync7,
78 mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
79 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
80 mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist,
81 pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3,
82 qdss_cti, qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3,
83 qup0_se4, qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1,
84 qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7,
85 qup2_se0, sailss_emac0, sailss_ospi, sail_top, sgmii_phy,
86 tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
87 tsense_pwm2, tsense_pwm3, tsense_pwm4, usb2phy_ac,
88 vsense_trigger ]
89
90 required:
91 - pins
92
93required:
94 - compatible
95 - reg
96
97unevaluatedProperties: false
98
99examples:
100 - |
101 #include <dt-bindings/interrupt-controller/arm-gic.h>
102
103 tlmm: pinctrl@f100000 {
104 compatible = "qcom,qcs8300-tlmm";
105 reg = <0x0f100000 0x300000>;
106 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
107 gpio-controller;
108 #gpio-cells = <2>;
109 gpio-ranges = <&tlmm 0 0 133>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112
113 qup-uart7-state {
114 pins = "gpio43", "gpio44";
115 function = "qup0_se7";
116 };
117 };
118...