tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/pgtable-3level-hwdef.h
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
9#define _ASM_PGTABLE_3LEVEL_HWDEF_H
10
11/*
12 * Hardware page table definitions.
13 *
14 * + Level 1/2 descriptor
15 * - common
16 */
17#define PUD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
18#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
19#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
20#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
21#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
22#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
23#define PMD_BIT4 (_AT(pmdval_t, 0))
24#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
25#define PMD_APTABLE_SHIFT (61)
26#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
27#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59)
28
29/*
30 * - section
31 */
32#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
33#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3)
34#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
35#define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */
36#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
37#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
38#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11)
39#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
40#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54)
41#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0))
42#define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
43#define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
44#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
45
46/*
47 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
48 */
49#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */
50#define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
51#define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
52#define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
53#define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
54#define PMD_SECT_CACHE_MASK (_AT(pmdval_t, 7) << 2)
55
56/*
57 * + Level 3 descriptor (PTE)
58 */
59#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
60#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
61#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
62#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
63#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
64#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
65#define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */
66#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
67#define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
68#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */
69#define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */
70#define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */
71
72/*
73 * 40-bit physical address supported.
74 */
75#define PHYS_MASK_SHIFT (40)
76#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
77
78#ifndef CONFIG_CPU_TTBR0_PAN
79/*
80 * TTBR0/TTBR1 split (PAGE_OFFSET):
81 * 0x40000000: T0SZ = 2, T1SZ = 0 (not used)
82 * 0x80000000: T0SZ = 0, T1SZ = 1
83 * 0xc0000000: T0SZ = 0, T1SZ = 2
84 *
85 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
86 * booting secondary CPUs would end up using TTBR1 for the identity
87 * mapping set up in TTBR0.
88 */
89#if defined CONFIG_VMSPLIT_2G
90#define TTBR1_OFFSET 16 /* skip two L1 entries */
91#elif defined CONFIG_VMSPLIT_3G
92#define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
93#else
94#define TTBR1_OFFSET 0
95#endif
96
97#define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16)
98#else
99/*
100 * With CONFIG_CPU_TTBR0_PAN enabled, TTBR1 is only used during uaccess
101 * disabled regions when TTBR0 is disabled.
102 */
103#define TTBR1_OFFSET 0 /* pointing to swapper_pg_dir */
104#define TTBR1_SIZE 0 /* TTBR1 size controlled via TTBCR.T0SZ */
105#endif
106
107/*
108 * TTBCR register bits.
109 *
110 * The ORGN0 and IRGN0 bits enables different forms of caching when
111 * walking the translation table. Clearing these bits (which is claimed
112 * to be the reset default) means "normal memory, [outer|inner]
113 * non-cacheable"
114 */
115#define TTBCR_EAE (1 << 31)
116#define TTBCR_IMP (1 << 30)
117#define TTBCR_SH1_MASK (3 << 28)
118#define TTBCR_ORGN1_MASK (3 << 26)
119#define TTBCR_IRGN1_MASK (3 << 24)
120#define TTBCR_EPD1 (1 << 23)
121#define TTBCR_A1 (1 << 22)
122#define TTBCR_T1SZ_MASK (7 << 16)
123#define TTBCR_SH0_MASK (3 << 12)
124#define TTBCR_ORGN0_MASK (3 << 10)
125#define TTBCR_IRGN0_MASK (3 << 8)
126#define TTBCR_EPD0 (1 << 7)
127#define TTBCR_T0SZ_MASK (7 << 0)
128
129#endif