tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023-2024, Linaro Ltd.
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/kernel.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/pm_runtime.h>
15
16#include <dt-bindings/clock/qcom,sm8750-dispcc.h>
17
18#include "common.h"
19#include "clk-alpha-pll.h"
20#include "clk-branch.h"
21#include "clk-pll.h"
22#include "clk-rcg.h"
23#include "clk-regmap.h"
24#include "clk-regmap-divider.h"
25#include "clk-regmap-mux.h"
26#include "reset.h"
27#include "gdsc.h"
28
29/* Need to match the order of clocks in DT binding */
30enum {
31 DT_BI_TCXO,
32 DT_BI_TCXO_AO,
33 DT_AHB_CLK,
34 DT_SLEEP_CLK,
35
36 DT_DSI0_PHY_PLL_OUT_BYTECLK,
37 DT_DSI0_PHY_PLL_OUT_DSICLK,
38 DT_DSI1_PHY_PLL_OUT_BYTECLK,
39 DT_DSI1_PHY_PLL_OUT_DSICLK,
40
41 DT_DP0_PHY_PLL_LINK_CLK,
42 DT_DP0_PHY_PLL_VCO_DIV_CLK,
43 DT_DP1_PHY_PLL_LINK_CLK,
44 DT_DP1_PHY_PLL_VCO_DIV_CLK,
45 DT_DP2_PHY_PLL_LINK_CLK,
46 DT_DP2_PHY_PLL_VCO_DIV_CLK,
47 DT_DP3_PHY_PLL_LINK_CLK,
48 DT_DP3_PHY_PLL_VCO_DIV_CLK,
49};
50
51#define DISP_CC_MISC_CMD 0xF000
52
53enum {
54 P_BI_TCXO,
55 P_DISP_CC_PLL0_OUT_MAIN,
56 P_DISP_CC_PLL1_OUT_EVEN,
57 P_DISP_CC_PLL1_OUT_MAIN,
58 P_DISP_CC_PLL2_OUT_MAIN,
59 P_DP0_PHY_PLL_LINK_CLK,
60 P_DP0_PHY_PLL_VCO_DIV_CLK,
61 P_DP1_PHY_PLL_LINK_CLK,
62 P_DP1_PHY_PLL_VCO_DIV_CLK,
63 P_DP2_PHY_PLL_LINK_CLK,
64 P_DP2_PHY_PLL_VCO_DIV_CLK,
65 P_DP3_PHY_PLL_LINK_CLK,
66 P_DP3_PHY_PLL_VCO_DIV_CLK,
67 P_DSI0_PHY_PLL_OUT_BYTECLK,
68 P_DSI0_PHY_PLL_OUT_DSICLK,
69 P_DSI1_PHY_PLL_OUT_BYTECLK,
70 P_DSI1_PHY_PLL_OUT_DSICLK,
71 P_SLEEP_CLK,
72};
73
74static const struct pll_vco pongo_elu_vco[] = {
75 { 38400000, 38400000, 0 },
76};
77
78static const struct pll_vco taycan_elu_vco[] = {
79 { 249600000, 2500000000, 0 },
80};
81
82static struct alpha_pll_config disp_cc_pll0_config = {
83 .l = 0xd,
84 .alpha = 0x6492,
85 .config_ctl_val = 0x19660387,
86 .config_ctl_hi_val = 0x098060a0,
87 .config_ctl_hi1_val = 0xb416cb20,
88 .user_ctl_val = 0x00000000,
89 .user_ctl_hi_val = 0x00000002,
90};
91
92static struct clk_alpha_pll disp_cc_pll0 = {
93 .offset = 0x0,
94 .vco_table = taycan_elu_vco,
95 .num_vco = ARRAY_SIZE(taycan_elu_vco),
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
97 .clkr = {
98 .hw.init = &(const struct clk_init_data) {
99 .name = "disp_cc_pll0",
100 .parent_data = &(const struct clk_parent_data) {
101 .index = DT_BI_TCXO,
102 },
103 .num_parents = 1,
104 .ops = &clk_alpha_pll_taycan_elu_ops,
105 },
106 },
107};
108
109static struct alpha_pll_config disp_cc_pll1_config = {
110 .l = 0x1f,
111 .alpha = 0x4000,
112 .config_ctl_val = 0x19660387,
113 .config_ctl_hi_val = 0x098060a0,
114 .config_ctl_hi1_val = 0xb416cb20,
115 .user_ctl_val = 0x00000000,
116 .user_ctl_hi_val = 0x00000002,
117};
118
119static struct clk_alpha_pll disp_cc_pll1 = {
120 .offset = 0x1000,
121 .vco_table = taycan_elu_vco,
122 .num_vco = ARRAY_SIZE(taycan_elu_vco),
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
124 .clkr = {
125 .hw.init = &(const struct clk_init_data) {
126 .name = "disp_cc_pll1",
127 .parent_data = &(const struct clk_parent_data) {
128 .index = DT_BI_TCXO,
129 },
130 .num_parents = 1,
131 .ops = &clk_alpha_pll_taycan_elu_ops,
132 },
133 },
134};
135
136static const struct alpha_pll_config disp_cc_pll2_config = {
137 .l = 0x493,
138 .alpha = 0x0,
139 .config_ctl_val = 0x60000f68,
140 .config_ctl_hi_val = 0x0001c808,
141 .config_ctl_hi1_val = 0x00000000,
142 .config_ctl_hi2_val = 0x040082f4,
143 .test_ctl_val = 0x00008000,
144 .test_ctl_hi_val = 0x0080c496,
145 .test_ctl_hi1_val = 0x40100180,
146 .test_ctl_hi2_val = 0x441001bc,
147 .test_ctl_hi3_val = 0x002003d8,
148 .user_ctl_val = 0x00000400,
149 .user_ctl_hi_val = 0x00e50302,
150};
151
152static struct clk_alpha_pll disp_cc_pll2 = {
153 .offset = 0x2000,
154 .vco_table = pongo_elu_vco,
155 .num_vco = ARRAY_SIZE(pongo_elu_vco),
156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_ELU],
157 .clkr = {
158 .hw.init = &(const struct clk_init_data) {
159 .name = "disp_cc_pll2",
160 .parent_data = &(const struct clk_parent_data) {
161 .index = DT_SLEEP_CLK,
162 },
163 .num_parents = 1,
164 .ops = &clk_alpha_pll_pongo_elu_ops,
165 },
166 },
167};
168
169static const struct parent_map disp_cc_parent_map_0[] = {
170 { P_BI_TCXO, 0 },
171};
172
173static const struct clk_parent_data disp_cc_parent_data_0[] = {
174 { .index = DT_BI_TCXO },
175};
176
177static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
178 { .index = DT_BI_TCXO_AO },
179};
180
181static const struct parent_map disp_cc_parent_map_1[] = {
182 { P_BI_TCXO, 0 },
183 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
184 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
185 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
186 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
187};
188
189static const struct clk_parent_data disp_cc_parent_data_1[] = {
190 { .index = DT_BI_TCXO },
191 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
192 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
193 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
194 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
195};
196
197static const struct parent_map disp_cc_parent_map_2[] = {
198 { P_BI_TCXO, 0 },
199 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
200 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
201 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
202};
203
204static const struct clk_parent_data disp_cc_parent_data_2[] = {
205 { .index = DT_BI_TCXO },
206 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
207 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
208 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
209};
210
211static const struct parent_map disp_cc_parent_map_3[] = {
212 { P_BI_TCXO, 0 },
213 { P_DP1_PHY_PLL_LINK_CLK, 2 },
214 { P_DP2_PHY_PLL_LINK_CLK, 3 },
215 { P_DP3_PHY_PLL_LINK_CLK, 4 },
216};
217
218static const struct clk_parent_data disp_cc_parent_data_3[] = {
219 { .index = DT_BI_TCXO },
220 { .index = DT_DP1_PHY_PLL_LINK_CLK },
221 { .index = DT_DP2_PHY_PLL_LINK_CLK },
222 { .index = DT_DP3_PHY_PLL_LINK_CLK },
223};
224
225static const struct parent_map disp_cc_parent_map_4[] = {
226 { P_BI_TCXO, 0 },
227 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
228 { P_DISP_CC_PLL2_OUT_MAIN, 2 },
229 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
230};
231
232static const struct clk_parent_data disp_cc_parent_data_4[] = {
233 { .index = DT_BI_TCXO },
234 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
235 { .hw = &disp_cc_pll2.clkr.hw },
236 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
237};
238
239static const struct parent_map disp_cc_parent_map_5[] = {
240 { P_BI_TCXO, 0 },
241 { P_DP0_PHY_PLL_LINK_CLK, 1 },
242 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
243 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
244 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
245 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
246};
247
248static const struct clk_parent_data disp_cc_parent_data_5[] = {
249 { .index = DT_BI_TCXO },
250 { .index = DT_DP0_PHY_PLL_LINK_CLK },
251 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
252 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
253 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
254 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
255};
256
257static const struct parent_map disp_cc_parent_map_6[] = {
258 { P_BI_TCXO, 0 },
259 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
260 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
261};
262
263static const struct clk_parent_data disp_cc_parent_data_6[] = {
264 { .index = DT_BI_TCXO },
265 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
266 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
267};
268
269static const struct parent_map disp_cc_parent_map_7[] = {
270 { P_BI_TCXO, 0 },
271 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
272 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
273};
274
275static const struct clk_parent_data disp_cc_parent_data_7[] = {
276 { .index = DT_BI_TCXO },
277 { .hw = &disp_cc_pll1.clkr.hw },
278 { .hw = &disp_cc_pll1.clkr.hw },
279};
280
281static const struct parent_map disp_cc_parent_map_8[] = {
282 { P_BI_TCXO, 0 },
283 { P_DP0_PHY_PLL_LINK_CLK, 1 },
284 { P_DP1_PHY_PLL_LINK_CLK, 2 },
285 { P_DP2_PHY_PLL_LINK_CLK, 3 },
286 { P_DP3_PHY_PLL_LINK_CLK, 4 },
287};
288
289static const struct clk_parent_data disp_cc_parent_data_8[] = {
290 { .index = DT_BI_TCXO },
291 { .index = DT_DP0_PHY_PLL_LINK_CLK },
292 { .index = DT_DP1_PHY_PLL_LINK_CLK },
293 { .index = DT_DP2_PHY_PLL_LINK_CLK },
294 { .index = DT_DP3_PHY_PLL_LINK_CLK },
295};
296
297static const struct parent_map disp_cc_parent_map_9[] = {
298 { P_BI_TCXO, 0 },
299 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
300 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
301 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
302};
303
304static const struct clk_parent_data disp_cc_parent_data_9[] = {
305 { .index = DT_BI_TCXO },
306 { .hw = &disp_cc_pll0.clkr.hw },
307 { .hw = &disp_cc_pll1.clkr.hw },
308 { .hw = &disp_cc_pll1.clkr.hw },
309};
310
311static const struct parent_map disp_cc_parent_map_10[] = {
312 { P_BI_TCXO, 0 },
313 { P_DISP_CC_PLL2_OUT_MAIN, 2 },
314};
315
316static const struct clk_parent_data disp_cc_parent_data_10[] = {
317 { .index = DT_BI_TCXO },
318 { .hw = &disp_cc_pll2.clkr.hw },
319};
320
321static const struct parent_map disp_cc_parent_map_11[] = {
322 { P_SLEEP_CLK, 0 },
323};
324
325static const struct clk_parent_data disp_cc_parent_data_11[] = {
326 { .index = DT_SLEEP_CLK },
327};
328
329static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = {
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 { }
332};
333
334static struct clk_rcg2 disp_cc_esync0_clk_src = {
335 .cmd_rcgr = 0x80c0,
336 .mnd_width = 16,
337 .hid_width = 5,
338 .parent_map = disp_cc_parent_map_4,
339 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
340 .clkr.hw.init = &(const struct clk_init_data) {
341 .name = "disp_cc_esync0_clk_src",
342 .parent_data = disp_cc_parent_data_4,
343 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
344 .flags = CLK_SET_RATE_PARENT,
345 .ops = &clk_byte2_ops,
346 },
347};
348
349static struct clk_rcg2 disp_cc_esync1_clk_src = {
350 .cmd_rcgr = 0x80d8,
351 .mnd_width = 16,
352 .hid_width = 5,
353 .parent_map = disp_cc_parent_map_4,
354 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
355 .clkr.hw.init = &(const struct clk_init_data) {
356 .name = "disp_cc_esync1_clk_src",
357 .parent_data = disp_cc_parent_data_4,
358 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
359 .flags = CLK_SET_RATE_PARENT,
360 .ops = &clk_byte2_ops,
361 },
362};
363
364static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
365 F(19200000, P_BI_TCXO, 1, 0, 0),
366 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
367 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
368 { }
369};
370
371static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
372 .cmd_rcgr = 0x8360,
373 .mnd_width = 0,
374 .hid_width = 5,
375 .parent_map = disp_cc_parent_map_7,
376 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
377 .clkr.hw.init = &(const struct clk_init_data) {
378 .name = "disp_cc_mdss_ahb_clk_src",
379 .parent_data = disp_cc_parent_data_7,
380 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
381 .flags = CLK_SET_RATE_PARENT,
382 .ops = &clk_rcg2_shared_ops,
383 },
384};
385
386static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
387 .cmd_rcgr = 0x8180,
388 .mnd_width = 0,
389 .hid_width = 5,
390 .parent_map = disp_cc_parent_map_1,
391 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
392 .clkr.hw.init = &(const struct clk_init_data) {
393 .name = "disp_cc_mdss_byte0_clk_src",
394 .parent_data = disp_cc_parent_data_1,
395 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
396 .flags = CLK_SET_RATE_PARENT,
397 .ops = &clk_byte2_ops,
398 },
399};
400
401static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
402 .cmd_rcgr = 0x819c,
403 .mnd_width = 0,
404 .hid_width = 5,
405 .parent_map = disp_cc_parent_map_1,
406 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
407 .clkr.hw.init = &(const struct clk_init_data) {
408 .name = "disp_cc_mdss_byte1_clk_src",
409 .parent_data = disp_cc_parent_data_1,
410 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
411 .flags = CLK_SET_RATE_PARENT,
412 .ops = &clk_byte2_ops,
413 },
414};
415
416static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
417 .cmd_rcgr = 0x8234,
418 .mnd_width = 0,
419 .hid_width = 5,
420 .parent_map = disp_cc_parent_map_0,
421 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
422 .clkr.hw.init = &(const struct clk_init_data) {
423 .name = "disp_cc_mdss_dptx0_aux_clk_src",
424 .parent_data = disp_cc_parent_data_0,
425 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
426 .flags = CLK_SET_RATE_PARENT,
427 .ops = &clk_rcg2_ops,
428 },
429};
430
431static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
432 .cmd_rcgr = 0x81e8,
433 .mnd_width = 0,
434 .hid_width = 5,
435 .parent_map = disp_cc_parent_map_8,
436 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
437 .clkr.hw.init = &(const struct clk_init_data) {
438 .name = "disp_cc_mdss_dptx0_link_clk_src",
439 .parent_data = disp_cc_parent_data_8,
440 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
441 .flags = CLK_SET_RATE_PARENT,
442 .ops = &clk_byte2_ops,
443 },
444};
445
446static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
447 .cmd_rcgr = 0x8204,
448 .mnd_width = 16,
449 .hid_width = 5,
450 .parent_map = disp_cc_parent_map_5,
451 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
452 .clkr.hw.init = &(const struct clk_init_data) {
453 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",
454 .parent_data = disp_cc_parent_data_5,
455 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
456 .flags = CLK_SET_RATE_PARENT,
457 .ops = &clk_dp_ops,
458 },
459};
460
461static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
462 .cmd_rcgr = 0x821c,
463 .mnd_width = 16,
464 .hid_width = 5,
465 .parent_map = disp_cc_parent_map_5,
466 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
467 .clkr.hw.init = &(const struct clk_init_data) {
468 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",
469 .parent_data = disp_cc_parent_data_5,
470 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
471 .flags = CLK_SET_RATE_PARENT,
472 .ops = &clk_dp_ops,
473 },
474};
475
476static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
477 .cmd_rcgr = 0x8298,
478 .mnd_width = 0,
479 .hid_width = 5,
480 .parent_map = disp_cc_parent_map_0,
481 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
482 .clkr.hw.init = &(const struct clk_init_data) {
483 .name = "disp_cc_mdss_dptx1_aux_clk_src",
484 .parent_data = disp_cc_parent_data_0,
485 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
486 .flags = CLK_SET_RATE_PARENT,
487 .ops = &clk_rcg2_ops,
488 },
489};
490
491static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
492 .cmd_rcgr = 0x827c,
493 .mnd_width = 0,
494 .hid_width = 5,
495 .parent_map = disp_cc_parent_map_3,
496 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
497 .clkr.hw.init = &(const struct clk_init_data) {
498 .name = "disp_cc_mdss_dptx1_link_clk_src",
499 .parent_data = disp_cc_parent_data_3,
500 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
501 .flags = CLK_SET_RATE_PARENT,
502 .ops = &clk_byte2_ops,
503 },
504};
505
506static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
507 .cmd_rcgr = 0x824c,
508 .mnd_width = 16,
509 .hid_width = 5,
510 .parent_map = disp_cc_parent_map_2,
511 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
512 .clkr.hw.init = &(const struct clk_init_data) {
513 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",
514 .parent_data = disp_cc_parent_data_2,
515 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
516 .flags = CLK_SET_RATE_PARENT,
517 .ops = &clk_dp_ops,
518 },
519};
520
521static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
522 .cmd_rcgr = 0x8264,
523 .mnd_width = 16,
524 .hid_width = 5,
525 .parent_map = disp_cc_parent_map_2,
526 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
527 .clkr.hw.init = &(const struct clk_init_data) {
528 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",
529 .parent_data = disp_cc_parent_data_2,
530 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
531 .flags = CLK_SET_RATE_PARENT,
532 .ops = &clk_dp_ops,
533 },
534};
535
536static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
537 .cmd_rcgr = 0x82fc,
538 .mnd_width = 0,
539 .hid_width = 5,
540 .parent_map = disp_cc_parent_map_0,
541 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
542 .clkr.hw.init = &(const struct clk_init_data) {
543 .name = "disp_cc_mdss_dptx2_aux_clk_src",
544 .parent_data = disp_cc_parent_data_0,
545 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
546 .flags = CLK_SET_RATE_PARENT,
547 .ops = &clk_rcg2_ops,
548 },
549};
550
551static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
552 .cmd_rcgr = 0x82b0,
553 .mnd_width = 0,
554 .hid_width = 5,
555 .parent_map = disp_cc_parent_map_3,
556 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
557 .clkr.hw.init = &(const struct clk_init_data) {
558 .name = "disp_cc_mdss_dptx2_link_clk_src",
559 .parent_data = disp_cc_parent_data_3,
560 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
561 .flags = CLK_SET_RATE_PARENT,
562 .ops = &clk_byte2_ops,
563 },
564};
565
566static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
567 .cmd_rcgr = 0x82cc,
568 .mnd_width = 16,
569 .hid_width = 5,
570 .parent_map = disp_cc_parent_map_2,
571 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
572 .clkr.hw.init = &(const struct clk_init_data) {
573 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",
574 .parent_data = disp_cc_parent_data_2,
575 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
576 .flags = CLK_SET_RATE_PARENT,
577 .ops = &clk_dp_ops,
578 },
579};
580
581static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
582 .cmd_rcgr = 0x82e4,
583 .mnd_width = 16,
584 .hid_width = 5,
585 .parent_map = disp_cc_parent_map_2,
586 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
587 .clkr.hw.init = &(const struct clk_init_data) {
588 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",
589 .parent_data = disp_cc_parent_data_2,
590 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
591 .flags = CLK_SET_RATE_PARENT,
592 .ops = &clk_dp_ops,
593 },
594};
595
596static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
597 .cmd_rcgr = 0x8348,
598 .mnd_width = 0,
599 .hid_width = 5,
600 .parent_map = disp_cc_parent_map_0,
601 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
602 .clkr.hw.init = &(const struct clk_init_data) {
603 .name = "disp_cc_mdss_dptx3_aux_clk_src",
604 .parent_data = disp_cc_parent_data_0,
605 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
606 .flags = CLK_SET_RATE_PARENT,
607 .ops = &clk_rcg2_ops,
608 },
609};
610
611static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
612 .cmd_rcgr = 0x832c,
613 .mnd_width = 0,
614 .hid_width = 5,
615 .parent_map = disp_cc_parent_map_3,
616 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
617 .clkr.hw.init = &(const struct clk_init_data) {
618 .name = "disp_cc_mdss_dptx3_link_clk_src",
619 .parent_data = disp_cc_parent_data_3,
620 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
621 .flags = CLK_SET_RATE_PARENT,
622 .ops = &clk_byte2_ops,
623 },
624};
625
626static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
627 .cmd_rcgr = 0x8314,
628 .mnd_width = 16,
629 .hid_width = 5,
630 .parent_map = disp_cc_parent_map_2,
631 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
632 .clkr.hw.init = &(const struct clk_init_data) {
633 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",
634 .parent_data = disp_cc_parent_data_2,
635 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
636 .flags = CLK_SET_RATE_PARENT,
637 .ops = &clk_dp_ops,
638 },
639};
640
641static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
642 .cmd_rcgr = 0x81b8,
643 .mnd_width = 0,
644 .hid_width = 5,
645 .parent_map = disp_cc_parent_map_6,
646 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
647 .clkr.hw.init = &(const struct clk_init_data) {
648 .name = "disp_cc_mdss_esc0_clk_src",
649 .parent_data = disp_cc_parent_data_6,
650 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
651 .flags = CLK_SET_RATE_PARENT,
652 .ops = &clk_rcg2_shared_ops,
653 },
654};
655
656static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
657 .cmd_rcgr = 0x81d0,
658 .mnd_width = 0,
659 .hid_width = 5,
660 .parent_map = disp_cc_parent_map_6,
661 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
662 .clkr.hw.init = &(const struct clk_init_data) {
663 .name = "disp_cc_mdss_esc1_clk_src",
664 .parent_data = disp_cc_parent_data_6,
665 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
666 .flags = CLK_SET_RATE_PARENT,
667 .ops = &clk_rcg2_shared_ops,
668 },
669};
670
671static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
672 F(19200000, P_BI_TCXO, 1, 0, 0),
673 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
674 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
675 F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
676 F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
677 F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
678 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
679 F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
680 F(575000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
681 { }
682};
683
684static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
685 .cmd_rcgr = 0x8150,
686 .mnd_width = 0,
687 .hid_width = 5,
688 .parent_map = disp_cc_parent_map_9,
689 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
690 .clkr.hw.init = &(const struct clk_init_data) {
691 .name = "disp_cc_mdss_mdp_clk_src",
692 .parent_data = disp_cc_parent_data_9,
693 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
694 .flags = CLK_SET_RATE_PARENT,
695 /*
696 * TODO: Downstream does not manage the clock directly, but
697 * places votes via new hardware block called "cesta".
698 * It is not clear whether such approach should be taken instead
699 * of manual control.
700 */
701 .ops = &clk_rcg2_shared_ops,
702 },
703};
704
705static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
706 .cmd_rcgr = 0x8108,
707 .mnd_width = 8,
708 .hid_width = 5,
709 .parent_map = disp_cc_parent_map_1,
710 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
711 .clkr.hw.init = &(const struct clk_init_data) {
712 .name = "disp_cc_mdss_pclk0_clk_src",
713 .parent_data = disp_cc_parent_data_1,
714 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
715 .flags = CLK_SET_RATE_PARENT,
716 .ops = &clk_pixel_ops,
717 },
718};
719
720static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
721 .cmd_rcgr = 0x8120,
722 .mnd_width = 8,
723 .hid_width = 5,
724 .parent_map = disp_cc_parent_map_1,
725 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
726 .clkr.hw.init = &(const struct clk_init_data) {
727 .name = "disp_cc_mdss_pclk1_clk_src",
728 .parent_data = disp_cc_parent_data_1,
729 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
730 .flags = CLK_SET_RATE_PARENT,
731 .ops = &clk_pixel_ops,
732 },
733};
734
735static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = {
736 .cmd_rcgr = 0x8138,
737 .mnd_width = 8,
738 .hid_width = 5,
739 .parent_map = disp_cc_parent_map_1,
740 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
741 .clkr.hw.init = &(const struct clk_init_data) {
742 .name = "disp_cc_mdss_pclk2_clk_src",
743 .parent_data = disp_cc_parent_data_1,
744 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
745 .flags = CLK_SET_RATE_PARENT,
746 .ops = &clk_pixel_ops,
747 },
748};
749
750static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
751 .cmd_rcgr = 0x8168,
752 .mnd_width = 0,
753 .hid_width = 5,
754 .parent_map = disp_cc_parent_map_0,
755 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
756 .clkr.hw.init = &(const struct clk_init_data) {
757 .name = "disp_cc_mdss_vsync_clk_src",
758 .parent_data = disp_cc_parent_data_0,
759 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
760 .flags = CLK_SET_RATE_PARENT,
761 .ops = &clk_rcg2_ops,
762 },
763};
764
765static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = {
766 F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0),
767 { }
768};
769
770static struct clk_rcg2 disp_cc_osc_clk_src = {
771 .cmd_rcgr = 0x80f0,
772 .mnd_width = 0,
773 .hid_width = 5,
774 .parent_map = disp_cc_parent_map_10,
775 .freq_tbl = ftbl_disp_cc_osc_clk_src,
776 .clkr.hw.init = &(const struct clk_init_data) {
777 .name = "disp_cc_osc_clk_src",
778 .parent_data = disp_cc_parent_data_10,
779 .num_parents = ARRAY_SIZE(disp_cc_parent_data_10),
780 .flags = CLK_SET_RATE_PARENT,
781 .ops = &clk_rcg2_ops,
782 },
783};
784
785static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
786 F(32000, P_SLEEP_CLK, 1, 0, 0),
787 { }
788};
789
790static struct clk_rcg2 disp_cc_sleep_clk_src = {
791 .cmd_rcgr = 0xe064,
792 .mnd_width = 0,
793 .hid_width = 5,
794 .parent_map = disp_cc_parent_map_11,
795 .freq_tbl = ftbl_disp_cc_sleep_clk_src,
796 .clkr.hw.init = &(const struct clk_init_data) {
797 .name = "disp_cc_sleep_clk_src",
798 .parent_data = disp_cc_parent_data_11,
799 .num_parents = ARRAY_SIZE(disp_cc_parent_data_11),
800 .flags = CLK_SET_RATE_PARENT,
801 .ops = &clk_rcg2_ops,
802 },
803};
804
805static struct clk_rcg2 disp_cc_xo_clk_src = {
806 .cmd_rcgr = 0xe044,
807 .mnd_width = 0,
808 .hid_width = 5,
809 .parent_map = disp_cc_parent_map_0,
810 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
811 .clkr.hw.init = &(const struct clk_init_data) {
812 .name = "disp_cc_xo_clk_src",
813 .parent_data = disp_cc_parent_data_0_ao,
814 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
815 .flags = CLK_SET_RATE_PARENT,
816 .ops = &clk_rcg2_ops,
817 },
818};
819
820static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
821 .reg = 0x8198,
822 .shift = 0,
823 .width = 4,
824 .clkr.hw.init = &(const struct clk_init_data) {
825 .name = "disp_cc_mdss_byte0_div_clk_src",
826 .parent_hws = (const struct clk_hw*[]) {
827 &disp_cc_mdss_byte0_clk_src.clkr.hw,
828 },
829 .num_parents = 1,
830 .flags = CLK_SET_RATE_PARENT,
831 .ops = &clk_regmap_div_ops,
832 },
833};
834
835static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
836 .reg = 0x81b4,
837 .shift = 0,
838 .width = 4,
839 .clkr.hw.init = &(const struct clk_init_data) {
840 .name = "disp_cc_mdss_byte1_div_clk_src",
841 .parent_hws = (const struct clk_hw*[]) {
842 &disp_cc_mdss_byte1_clk_src.clkr.hw,
843 },
844 .num_parents = 1,
845 .flags = CLK_SET_RATE_PARENT,
846 .ops = &clk_regmap_div_ops,
847 },
848};
849
850static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
851 .reg = 0x8200,
852 .shift = 0,
853 .width = 4,
854 .clkr.hw.init = &(const struct clk_init_data) {
855 .name = "disp_cc_mdss_dptx0_link_div_clk_src",
856 .parent_hws = (const struct clk_hw*[]) {
857 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
858 },
859 .num_parents = 1,
860 .flags = CLK_SET_RATE_PARENT,
861 .ops = &clk_regmap_div_ro_ops,
862 },
863};
864
865static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
866 .reg = 0x8294,
867 .shift = 0,
868 .width = 4,
869 .clkr.hw.init = &(const struct clk_init_data) {
870 .name = "disp_cc_mdss_dptx1_link_div_clk_src",
871 .parent_hws = (const struct clk_hw*[]) {
872 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
873 },
874 .num_parents = 1,
875 .flags = CLK_SET_RATE_PARENT,
876 .ops = &clk_regmap_div_ro_ops,
877 },
878};
879
880static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
881 .reg = 0x82c8,
882 .shift = 0,
883 .width = 4,
884 .clkr.hw.init = &(const struct clk_init_data) {
885 .name = "disp_cc_mdss_dptx2_link_div_clk_src",
886 .parent_hws = (const struct clk_hw*[]) {
887 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
888 },
889 .num_parents = 1,
890 .flags = CLK_SET_RATE_PARENT,
891 .ops = &clk_regmap_div_ro_ops,
892 },
893};
894
895static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
896 .reg = 0x8344,
897 .shift = 0,
898 .width = 4,
899 .clkr.hw.init = &(const struct clk_init_data) {
900 .name = "disp_cc_mdss_dptx3_link_div_clk_src",
901 .parent_hws = (const struct clk_hw*[]) {
902 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
903 },
904 .num_parents = 1,
905 .flags = CLK_SET_RATE_PARENT,
906 .ops = &clk_regmap_div_ro_ops,
907 },
908};
909
910static struct clk_branch disp_cc_esync0_clk = {
911 .halt_reg = 0x80b8,
912 .halt_check = BRANCH_HALT,
913 .clkr = {
914 .enable_reg = 0x80b8,
915 .enable_mask = BIT(0),
916 .hw.init = &(const struct clk_init_data) {
917 .name = "disp_cc_esync0_clk",
918 .parent_hws = (const struct clk_hw*[]) {
919 &disp_cc_esync0_clk_src.clkr.hw,
920 },
921 .num_parents = 1,
922 .flags = CLK_SET_RATE_PARENT,
923 .ops = &clk_branch2_ops,
924 },
925 },
926};
927
928static struct clk_branch disp_cc_esync1_clk = {
929 .halt_reg = 0x80bc,
930 .halt_check = BRANCH_HALT,
931 .clkr = {
932 .enable_reg = 0x80bc,
933 .enable_mask = BIT(0),
934 .hw.init = &(const struct clk_init_data) {
935 .name = "disp_cc_esync1_clk",
936 .parent_hws = (const struct clk_hw*[]) {
937 &disp_cc_esync1_clk_src.clkr.hw,
938 },
939 .num_parents = 1,
940 .flags = CLK_SET_RATE_PARENT,
941 .ops = &clk_branch2_ops,
942 },
943 },
944};
945
946static struct clk_branch disp_cc_mdss_accu_shift_clk = {
947 .halt_reg = 0xe060,
948 .halt_check = BRANCH_HALT_VOTED,
949 .clkr = {
950 .enable_reg = 0xe060,
951 .enable_mask = BIT(0),
952 .hw.init = &(const struct clk_init_data) {
953 .name = "disp_cc_mdss_accu_shift_clk",
954 .parent_hws = (const struct clk_hw*[]) {
955 &disp_cc_xo_clk_src.clkr.hw,
956 },
957 .num_parents = 1,
958 .flags = CLK_SET_RATE_PARENT,
959 .ops = &clk_branch2_ops,
960 },
961 },
962};
963
964static struct clk_branch disp_cc_mdss_ahb1_clk = {
965 .halt_reg = 0xa028,
966 .halt_check = BRANCH_HALT,
967 .clkr = {
968 .enable_reg = 0xa028,
969 .enable_mask = BIT(0),
970 .hw.init = &(const struct clk_init_data) {
971 .name = "disp_cc_mdss_ahb1_clk",
972 .parent_hws = (const struct clk_hw*[]) {
973 &disp_cc_mdss_ahb_clk_src.clkr.hw,
974 },
975 .num_parents = 1,
976 .flags = CLK_SET_RATE_PARENT,
977 .ops = &clk_branch2_ops,
978 },
979 },
980};
981
982static struct clk_branch disp_cc_mdss_ahb_clk = {
983 .halt_reg = 0x80b0,
984 .halt_check = BRANCH_HALT,
985 .clkr = {
986 .enable_reg = 0x80b0,
987 .enable_mask = BIT(0),
988 .hw.init = &(const struct clk_init_data) {
989 .name = "disp_cc_mdss_ahb_clk",
990 .parent_hws = (const struct clk_hw*[]) {
991 &disp_cc_mdss_ahb_clk_src.clkr.hw,
992 },
993 .num_parents = 1,
994 .flags = CLK_SET_RATE_PARENT,
995 .ops = &clk_branch2_ops,
996 },
997 },
998};
999
1000static struct clk_branch disp_cc_mdss_byte0_clk = {
1001 .halt_reg = 0x8034,
1002 .halt_check = BRANCH_HALT,
1003 .clkr = {
1004 .enable_reg = 0x8034,
1005 .enable_mask = BIT(0),
1006 .hw.init = &(const struct clk_init_data) {
1007 .name = "disp_cc_mdss_byte0_clk",
1008 .parent_hws = (const struct clk_hw*[]) {
1009 &disp_cc_mdss_byte0_clk_src.clkr.hw,
1010 },
1011 .num_parents = 1,
1012 .flags = CLK_SET_RATE_PARENT,
1013 .ops = &clk_branch2_ops,
1014 },
1015 },
1016};
1017
1018static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
1019 .halt_reg = 0x8038,
1020 .halt_check = BRANCH_HALT,
1021 .clkr = {
1022 .enable_reg = 0x8038,
1023 .enable_mask = BIT(0),
1024 .hw.init = &(const struct clk_init_data) {
1025 .name = "disp_cc_mdss_byte0_intf_clk",
1026 .parent_hws = (const struct clk_hw*[]) {
1027 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
1028 },
1029 .num_parents = 1,
1030 .flags = CLK_SET_RATE_PARENT,
1031 .ops = &clk_branch2_ops,
1032 },
1033 },
1034};
1035
1036static struct clk_branch disp_cc_mdss_byte1_clk = {
1037 .halt_reg = 0x803c,
1038 .halt_check = BRANCH_HALT,
1039 .clkr = {
1040 .enable_reg = 0x803c,
1041 .enable_mask = BIT(0),
1042 .hw.init = &(const struct clk_init_data) {
1043 .name = "disp_cc_mdss_byte1_clk",
1044 .parent_hws = (const struct clk_hw*[]) {
1045 &disp_cc_mdss_byte1_clk_src.clkr.hw,
1046 },
1047 .num_parents = 1,
1048 .flags = CLK_SET_RATE_PARENT,
1049 .ops = &clk_branch2_ops,
1050 },
1051 },
1052};
1053
1054static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
1055 .halt_reg = 0x8040,
1056 .halt_check = BRANCH_HALT,
1057 .clkr = {
1058 .enable_reg = 0x8040,
1059 .enable_mask = BIT(0),
1060 .hw.init = &(const struct clk_init_data) {
1061 .name = "disp_cc_mdss_byte1_intf_clk",
1062 .parent_hws = (const struct clk_hw*[]) {
1063 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
1064 },
1065 .num_parents = 1,
1066 .flags = CLK_SET_RATE_PARENT,
1067 .ops = &clk_branch2_ops,
1068 },
1069 },
1070};
1071
1072static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
1073 .halt_reg = 0x8064,
1074 .halt_check = BRANCH_HALT,
1075 .clkr = {
1076 .enable_reg = 0x8064,
1077 .enable_mask = BIT(0),
1078 .hw.init = &(const struct clk_init_data) {
1079 .name = "disp_cc_mdss_dptx0_aux_clk",
1080 .parent_hws = (const struct clk_hw*[]) {
1081 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1082 },
1083 .num_parents = 1,
1084 .flags = CLK_SET_RATE_PARENT,
1085 .ops = &clk_branch2_ops,
1086 },
1087 },
1088};
1089
1090static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
1091 .halt_reg = 0x8058,
1092 .halt_check = BRANCH_HALT,
1093 .clkr = {
1094 .enable_reg = 0x8058,
1095 .enable_mask = BIT(0),
1096 .hw.init = &(const struct clk_init_data) {
1097 .name = "disp_cc_mdss_dptx0_crypto_clk",
1098 .parent_hws = (const struct clk_hw*[]) {
1099 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1100 },
1101 .num_parents = 1,
1102 .flags = CLK_SET_RATE_PARENT,
1103 .ops = &clk_branch2_ops,
1104 },
1105 },
1106};
1107
1108static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
1109 .halt_reg = 0x804c,
1110 .halt_check = BRANCH_HALT,
1111 .clkr = {
1112 .enable_reg = 0x804c,
1113 .enable_mask = BIT(0),
1114 .hw.init = &(const struct clk_init_data) {
1115 .name = "disp_cc_mdss_dptx0_link_clk",
1116 .parent_hws = (const struct clk_hw*[]) {
1117 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1118 },
1119 .num_parents = 1,
1120 .flags = CLK_SET_RATE_PARENT,
1121 .ops = &clk_branch2_ops,
1122 },
1123 },
1124};
1125
1126static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
1127 .halt_reg = 0x8054,
1128 .halt_check = BRANCH_HALT,
1129 .clkr = {
1130 .enable_reg = 0x8054,
1131 .enable_mask = BIT(0),
1132 .hw.init = &(const struct clk_init_data) {
1133 .name = "disp_cc_mdss_dptx0_link_intf_clk",
1134 .parent_hws = (const struct clk_hw*[]) {
1135 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1136 },
1137 .num_parents = 1,
1138 .flags = CLK_SET_RATE_PARENT,
1139 .ops = &clk_branch2_ops,
1140 },
1141 },
1142};
1143
1144static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
1145 .halt_reg = 0x805c,
1146 .halt_check = BRANCH_HALT,
1147 .clkr = {
1148 .enable_reg = 0x805c,
1149 .enable_mask = BIT(0),
1150 .hw.init = &(const struct clk_init_data) {
1151 .name = "disp_cc_mdss_dptx0_pixel0_clk",
1152 .parent_hws = (const struct clk_hw*[]) {
1153 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1154 },
1155 .num_parents = 1,
1156 .flags = CLK_SET_RATE_PARENT,
1157 .ops = &clk_branch2_ops,
1158 },
1159 },
1160};
1161
1162static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1163 .halt_reg = 0x8060,
1164 .halt_check = BRANCH_HALT,
1165 .clkr = {
1166 .enable_reg = 0x8060,
1167 .enable_mask = BIT(0),
1168 .hw.init = &(const struct clk_init_data) {
1169 .name = "disp_cc_mdss_dptx0_pixel1_clk",
1170 .parent_hws = (const struct clk_hw*[]) {
1171 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1172 },
1173 .num_parents = 1,
1174 .flags = CLK_SET_RATE_PARENT,
1175 .ops = &clk_branch2_ops,
1176 },
1177 },
1178};
1179
1180static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1181 .halt_reg = 0x8050,
1182 .halt_check = BRANCH_HALT,
1183 .clkr = {
1184 .enable_reg = 0x8050,
1185 .enable_mask = BIT(0),
1186 .hw.init = &(const struct clk_init_data) {
1187 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1188 .parent_hws = (const struct clk_hw*[]) {
1189 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1190 },
1191 .num_parents = 1,
1192 .flags = CLK_SET_RATE_PARENT,
1193 .ops = &clk_branch2_ops,
1194 },
1195 },
1196};
1197
1198static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1199 .halt_reg = 0x8080,
1200 .halt_check = BRANCH_HALT,
1201 .clkr = {
1202 .enable_reg = 0x8080,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(const struct clk_init_data) {
1205 .name = "disp_cc_mdss_dptx1_aux_clk",
1206 .parent_hws = (const struct clk_hw*[]) {
1207 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1208 },
1209 .num_parents = 1,
1210 .flags = CLK_SET_RATE_PARENT,
1211 .ops = &clk_branch2_ops,
1212 },
1213 },
1214};
1215
1216static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1217 .halt_reg = 0x807c,
1218 .halt_check = BRANCH_HALT,
1219 .clkr = {
1220 .enable_reg = 0x807c,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(const struct clk_init_data) {
1223 .name = "disp_cc_mdss_dptx1_crypto_clk",
1224 .parent_hws = (const struct clk_hw*[]) {
1225 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1226 },
1227 .num_parents = 1,
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1230 },
1231 },
1232};
1233
1234static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1235 .halt_reg = 0x8070,
1236 .halt_check = BRANCH_HALT,
1237 .clkr = {
1238 .enable_reg = 0x8070,
1239 .enable_mask = BIT(0),
1240 .hw.init = &(const struct clk_init_data) {
1241 .name = "disp_cc_mdss_dptx1_link_clk",
1242 .parent_hws = (const struct clk_hw*[]) {
1243 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1244 },
1245 .num_parents = 1,
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250};
1251
1252static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1253 .halt_reg = 0x8078,
1254 .halt_check = BRANCH_HALT,
1255 .clkr = {
1256 .enable_reg = 0x8078,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(const struct clk_init_data) {
1259 .name = "disp_cc_mdss_dptx1_link_intf_clk",
1260 .parent_hws = (const struct clk_hw*[]) {
1261 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1262 },
1263 .num_parents = 1,
1264 .flags = CLK_SET_RATE_PARENT,
1265 .ops = &clk_branch2_ops,
1266 },
1267 },
1268};
1269
1270static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1271 .halt_reg = 0x8068,
1272 .halt_check = BRANCH_HALT,
1273 .clkr = {
1274 .enable_reg = 0x8068,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(const struct clk_init_data) {
1277 .name = "disp_cc_mdss_dptx1_pixel0_clk",
1278 .parent_hws = (const struct clk_hw*[]) {
1279 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1280 },
1281 .num_parents = 1,
1282 .flags = CLK_SET_RATE_PARENT,
1283 .ops = &clk_branch2_ops,
1284 },
1285 },
1286};
1287
1288static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1289 .halt_reg = 0x806c,
1290 .halt_check = BRANCH_HALT,
1291 .clkr = {
1292 .enable_reg = 0x806c,
1293 .enable_mask = BIT(0),
1294 .hw.init = &(const struct clk_init_data) {
1295 .name = "disp_cc_mdss_dptx1_pixel1_clk",
1296 .parent_hws = (const struct clk_hw*[]) {
1297 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1298 },
1299 .num_parents = 1,
1300 .flags = CLK_SET_RATE_PARENT,
1301 .ops = &clk_branch2_ops,
1302 },
1303 },
1304};
1305
1306static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1307 .halt_reg = 0x8074,
1308 .halt_check = BRANCH_HALT,
1309 .clkr = {
1310 .enable_reg = 0x8074,
1311 .enable_mask = BIT(0),
1312 .hw.init = &(const struct clk_init_data) {
1313 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1314 .parent_hws = (const struct clk_hw*[]) {
1315 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1316 },
1317 .num_parents = 1,
1318 .flags = CLK_SET_RATE_PARENT,
1319 .ops = &clk_branch2_ops,
1320 },
1321 },
1322};
1323
1324static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1325 .halt_reg = 0x8098,
1326 .halt_check = BRANCH_HALT,
1327 .clkr = {
1328 .enable_reg = 0x8098,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(const struct clk_init_data) {
1331 .name = "disp_cc_mdss_dptx2_aux_clk",
1332 .parent_hws = (const struct clk_hw*[]) {
1333 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1334 },
1335 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1338 },
1339 },
1340};
1341
1342static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1343 .halt_reg = 0x8094,
1344 .halt_check = BRANCH_HALT,
1345 .clkr = {
1346 .enable_reg = 0x8094,
1347 .enable_mask = BIT(0),
1348 .hw.init = &(const struct clk_init_data) {
1349 .name = "disp_cc_mdss_dptx2_crypto_clk",
1350 .parent_hws = (const struct clk_hw*[]) {
1351 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1352 },
1353 .num_parents = 1,
1354 .flags = CLK_SET_RATE_PARENT,
1355 .ops = &clk_branch2_ops,
1356 },
1357 },
1358};
1359
1360static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1361 .halt_reg = 0x808c,
1362 .halt_check = BRANCH_HALT,
1363 .clkr = {
1364 .enable_reg = 0x808c,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(const struct clk_init_data) {
1367 .name = "disp_cc_mdss_dptx2_link_clk",
1368 .parent_hws = (const struct clk_hw*[]) {
1369 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376};
1377
1378static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1379 .halt_reg = 0x8090,
1380 .halt_check = BRANCH_HALT,
1381 .clkr = {
1382 .enable_reg = 0x8090,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(const struct clk_init_data) {
1385 .name = "disp_cc_mdss_dptx2_link_intf_clk",
1386 .parent_hws = (const struct clk_hw*[]) {
1387 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1388 },
1389 .num_parents = 1,
1390 .flags = CLK_SET_RATE_PARENT,
1391 .ops = &clk_branch2_ops,
1392 },
1393 },
1394};
1395
1396static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1397 .halt_reg = 0x8084,
1398 .halt_check = BRANCH_HALT,
1399 .clkr = {
1400 .enable_reg = 0x8084,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(const struct clk_init_data) {
1403 .name = "disp_cc_mdss_dptx2_pixel0_clk",
1404 .parent_hws = (const struct clk_hw*[]) {
1405 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1406 },
1407 .num_parents = 1,
1408 .flags = CLK_SET_RATE_PARENT,
1409 .ops = &clk_branch2_ops,
1410 },
1411 },
1412};
1413
1414static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1415 .halt_reg = 0x8088,
1416 .halt_check = BRANCH_HALT,
1417 .clkr = {
1418 .enable_reg = 0x8088,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(const struct clk_init_data) {
1421 .name = "disp_cc_mdss_dptx2_pixel1_clk",
1422 .parent_hws = (const struct clk_hw*[]) {
1423 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1424 },
1425 .num_parents = 1,
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1428 },
1429 },
1430};
1431
1432static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1433 .halt_reg = 0x80a8,
1434 .halt_check = BRANCH_HALT,
1435 .clkr = {
1436 .enable_reg = 0x80a8,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(const struct clk_init_data) {
1439 .name = "disp_cc_mdss_dptx3_aux_clk",
1440 .parent_hws = (const struct clk_hw*[]) {
1441 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1442 },
1443 .num_parents = 1,
1444 .flags = CLK_SET_RATE_PARENT,
1445 .ops = &clk_branch2_ops,
1446 },
1447 },
1448};
1449
1450static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1451 .halt_reg = 0x80ac,
1452 .halt_check = BRANCH_HALT,
1453 .clkr = {
1454 .enable_reg = 0x80ac,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(const struct clk_init_data) {
1457 .name = "disp_cc_mdss_dptx3_crypto_clk",
1458 .parent_hws = (const struct clk_hw*[]) {
1459 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1460 },
1461 .num_parents = 1,
1462 .flags = CLK_SET_RATE_PARENT,
1463 .ops = &clk_branch2_ops,
1464 },
1465 },
1466};
1467
1468static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1469 .halt_reg = 0x80a0,
1470 .halt_check = BRANCH_HALT,
1471 .clkr = {
1472 .enable_reg = 0x80a0,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(const struct clk_init_data) {
1475 .name = "disp_cc_mdss_dptx3_link_clk",
1476 .parent_hws = (const struct clk_hw*[]) {
1477 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1478 },
1479 .num_parents = 1,
1480 .flags = CLK_SET_RATE_PARENT,
1481 .ops = &clk_branch2_ops,
1482 },
1483 },
1484};
1485
1486static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1487 .halt_reg = 0x80a4,
1488 .halt_check = BRANCH_HALT,
1489 .clkr = {
1490 .enable_reg = 0x80a4,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(const struct clk_init_data) {
1493 .name = "disp_cc_mdss_dptx3_link_intf_clk",
1494 .parent_hws = (const struct clk_hw*[]) {
1495 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1496 },
1497 .num_parents = 1,
1498 .flags = CLK_SET_RATE_PARENT,
1499 .ops = &clk_branch2_ops,
1500 },
1501 },
1502};
1503
1504static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1505 .halt_reg = 0x809c,
1506 .halt_check = BRANCH_HALT,
1507 .clkr = {
1508 .enable_reg = 0x809c,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(const struct clk_init_data) {
1511 .name = "disp_cc_mdss_dptx3_pixel0_clk",
1512 .parent_hws = (const struct clk_hw*[]) {
1513 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1514 },
1515 .num_parents = 1,
1516 .flags = CLK_SET_RATE_PARENT,
1517 .ops = &clk_branch2_ops,
1518 },
1519 },
1520};
1521
1522static struct clk_branch disp_cc_mdss_esc0_clk = {
1523 .halt_reg = 0x8044,
1524 .halt_check = BRANCH_HALT,
1525 .clkr = {
1526 .enable_reg = 0x8044,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(const struct clk_init_data) {
1529 .name = "disp_cc_mdss_esc0_clk",
1530 .parent_hws = (const struct clk_hw*[]) {
1531 &disp_cc_mdss_esc0_clk_src.clkr.hw,
1532 },
1533 .num_parents = 1,
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1536 },
1537 },
1538};
1539
1540static struct clk_branch disp_cc_mdss_esc1_clk = {
1541 .halt_reg = 0x8048,
1542 .halt_check = BRANCH_HALT,
1543 .clkr = {
1544 .enable_reg = 0x8048,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(const struct clk_init_data) {
1547 .name = "disp_cc_mdss_esc1_clk",
1548 .parent_hws = (const struct clk_hw*[]) {
1549 &disp_cc_mdss_esc1_clk_src.clkr.hw,
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556};
1557
1558static struct clk_branch disp_cc_mdss_mdp1_clk = {
1559 .halt_reg = 0xa004,
1560 .halt_check = BRANCH_HALT,
1561 .clkr = {
1562 .enable_reg = 0xa004,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(const struct clk_init_data) {
1565 .name = "disp_cc_mdss_mdp1_clk",
1566 .parent_hws = (const struct clk_hw*[]) {
1567 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1568 },
1569 .num_parents = 1,
1570 .flags = CLK_SET_RATE_PARENT,
1571 .ops = &clk_branch2_ops,
1572 },
1573 },
1574};
1575
1576static struct clk_branch disp_cc_mdss_mdp_clk = {
1577 .halt_reg = 0x8010,
1578 .halt_check = BRANCH_HALT,
1579 .clkr = {
1580 .enable_reg = 0x8010,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(const struct clk_init_data) {
1583 .name = "disp_cc_mdss_mdp_clk",
1584 .parent_hws = (const struct clk_hw*[]) {
1585 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1586 },
1587 .num_parents = 1,
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_aon_ops,
1590 },
1591 },
1592};
1593
1594static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1595 .halt_reg = 0xa014,
1596 .halt_check = BRANCH_HALT,
1597 .clkr = {
1598 .enable_reg = 0xa014,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(const struct clk_init_data) {
1601 .name = "disp_cc_mdss_mdp_lut1_clk",
1602 .parent_hws = (const struct clk_hw*[]) {
1603 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1613 .halt_reg = 0x8020,
1614 .halt_check = BRANCH_HALT_VOTED,
1615 .clkr = {
1616 .enable_reg = 0x8020,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(const struct clk_init_data) {
1619 .name = "disp_cc_mdss_mdp_lut_clk",
1620 .parent_hws = (const struct clk_hw*[]) {
1621 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1622 },
1623 .num_parents = 1,
1624 .flags = CLK_SET_RATE_PARENT,
1625 .ops = &clk_branch2_ops,
1626 },
1627 },
1628};
1629
1630static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1631 .halt_reg = 0xc004,
1632 .halt_check = BRANCH_HALT_VOTED,
1633 .clkr = {
1634 .enable_reg = 0xc004,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(const struct clk_init_data) {
1637 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1638 .parent_hws = (const struct clk_hw*[]) {
1639 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch disp_cc_mdss_pclk0_clk = {
1649 .halt_reg = 0x8004,
1650 .halt_check = BRANCH_HALT,
1651 .clkr = {
1652 .enable_reg = 0x8004,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(const struct clk_init_data) {
1655 .name = "disp_cc_mdss_pclk0_clk",
1656 .parent_hws = (const struct clk_hw*[]) {
1657 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1658 },
1659 .num_parents = 1,
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_branch2_ops,
1662 },
1663 },
1664};
1665
1666static struct clk_branch disp_cc_mdss_pclk1_clk = {
1667 .halt_reg = 0x8008,
1668 .halt_check = BRANCH_HALT,
1669 .clkr = {
1670 .enable_reg = 0x8008,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(const struct clk_init_data) {
1673 .name = "disp_cc_mdss_pclk1_clk",
1674 .parent_hws = (const struct clk_hw*[]) {
1675 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1676 },
1677 .num_parents = 1,
1678 .flags = CLK_SET_RATE_PARENT,
1679 .ops = &clk_branch2_ops,
1680 },
1681 },
1682};
1683
1684static struct clk_branch disp_cc_mdss_pclk2_clk = {
1685 .halt_reg = 0x800c,
1686 .halt_check = BRANCH_HALT,
1687 .clkr = {
1688 .enable_reg = 0x800c,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(const struct clk_init_data) {
1691 .name = "disp_cc_mdss_pclk2_clk",
1692 .parent_hws = (const struct clk_hw*[]) {
1693 &disp_cc_mdss_pclk2_clk_src.clkr.hw,
1694 },
1695 .num_parents = 1,
1696 .flags = CLK_SET_RATE_PARENT,
1697 .ops = &clk_branch2_ops,
1698 },
1699 },
1700};
1701
1702static struct clk_branch disp_cc_mdss_vsync1_clk = {
1703 .halt_reg = 0xa024,
1704 .halt_check = BRANCH_HALT,
1705 .clkr = {
1706 .enable_reg = 0xa024,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(const struct clk_init_data) {
1709 .name = "disp_cc_mdss_vsync1_clk",
1710 .parent_hws = (const struct clk_hw*[]) {
1711 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1712 },
1713 .num_parents = 1,
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718};
1719
1720static struct clk_branch disp_cc_mdss_vsync_clk = {
1721 .halt_reg = 0x8030,
1722 .halt_check = BRANCH_HALT,
1723 .clkr = {
1724 .enable_reg = 0x8030,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(const struct clk_init_data) {
1727 .name = "disp_cc_mdss_vsync_clk",
1728 .parent_hws = (const struct clk_hw*[]) {
1729 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1730 },
1731 .num_parents = 1,
1732 .flags = CLK_SET_RATE_PARENT,
1733 .ops = &clk_branch2_ops,
1734 },
1735 },
1736};
1737
1738static struct clk_branch disp_cc_osc_clk = {
1739 .halt_reg = 0x80b4,
1740 .halt_check = BRANCH_HALT,
1741 .clkr = {
1742 .enable_reg = 0x80b4,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(const struct clk_init_data) {
1745 .name = "disp_cc_osc_clk",
1746 .parent_hws = (const struct clk_hw*[]) {
1747 &disp_cc_osc_clk_src.clkr.hw,
1748 },
1749 .num_parents = 1,
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_branch2_ops,
1752 },
1753 },
1754};
1755
1756static struct gdsc mdss_gdsc = {
1757 .gdscr = 0x9000,
1758 .en_rest_wait_val = 0x2,
1759 .en_few_wait_val = 0x2,
1760 .clk_dis_wait_val = 0xf,
1761 .pd = {
1762 .name = "mdss_gdsc",
1763 },
1764 .pwrsts = PWRSTS_OFF_ON,
1765 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1766};
1767
1768static struct gdsc mdss_int2_gdsc = {
1769 .gdscr = 0xb000,
1770 .en_rest_wait_val = 0x2,
1771 .en_few_wait_val = 0x2,
1772 .clk_dis_wait_val = 0xf,
1773 .pd = {
1774 .name = "mdss_int2_gdsc",
1775 },
1776 .pwrsts = PWRSTS_OFF_ON,
1777 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1778};
1779
1780static struct clk_regmap *disp_cc_sm8750_clocks[] = {
1781 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr,
1782 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr,
1783 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr,
1784 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr,
1785 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr,
1786 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1787 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1788 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1789 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1790 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1791 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1792 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1793 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1794 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1795 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1796 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1797 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1798 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1799 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1800 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1801 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1802 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1803 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1804 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1805 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1806 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1807 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1808 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1809 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1810 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1811 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1812 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1813 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1814 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1815 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1816 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1817 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1818 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1819 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1820 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1821 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1822 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1823 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1824 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1825 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1826 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1827 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1828 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1829 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1830 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1831 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1832 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1833 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1834 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1835 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1836 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1837 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1838 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1839 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1840 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1841 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1842 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1843 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1844 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1845 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1846 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1847 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1848 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1849 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1850 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1851 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1852 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1853 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1854 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1855 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1856 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1857 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr,
1858 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr,
1859 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1860 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1861 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1862 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr,
1863 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr,
1864 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1865 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1866 [DISP_CC_PLL2] = &disp_cc_pll2.clkr,
1867 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1868 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1869};
1870
1871static const struct qcom_reset_map disp_cc_sm8750_resets[] = {
1872 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1873 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1874 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1875};
1876
1877static struct gdsc *disp_cc_sm8750_gdscs[] = {
1878 [MDSS_GDSC] = &mdss_gdsc,
1879 [MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1880};
1881
1882static const struct regmap_config disp_cc_sm8750_regmap_config = {
1883 .reg_bits = 32,
1884 .reg_stride = 4,
1885 .val_bits = 32,
1886 .max_register = 0x11014,
1887 .fast_io = true,
1888};
1889
1890static struct qcom_cc_desc disp_cc_sm8750_desc = {
1891 .config = &disp_cc_sm8750_regmap_config,
1892 .clks = disp_cc_sm8750_clocks,
1893 .num_clks = ARRAY_SIZE(disp_cc_sm8750_clocks),
1894 .resets = disp_cc_sm8750_resets,
1895 .num_resets = ARRAY_SIZE(disp_cc_sm8750_resets),
1896 .gdscs = disp_cc_sm8750_gdscs,
1897 .num_gdscs = ARRAY_SIZE(disp_cc_sm8750_gdscs),
1898};
1899
1900static const struct of_device_id disp_cc_sm8750_match_table[] = {
1901 { .compatible = "qcom,sm8750-dispcc" },
1902 { }
1903};
1904MODULE_DEVICE_TABLE(of, disp_cc_sm8750_match_table);
1905
1906static int disp_cc_sm8750_probe(struct platform_device *pdev)
1907{
1908 struct regmap *regmap;
1909 int ret;
1910
1911 ret = devm_pm_runtime_enable(&pdev->dev);
1912 if (ret)
1913 return ret;
1914
1915 ret = pm_runtime_resume_and_get(&pdev->dev);
1916 if (ret)
1917 return ret;
1918
1919 regmap = qcom_cc_map(pdev, &disp_cc_sm8750_desc);
1920 if (IS_ERR(regmap)) {
1921 ret = PTR_ERR(regmap);
1922 goto err_put_rpm;
1923 }
1924
1925 clk_taycan_elu_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1926 clk_taycan_elu_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1927 clk_pongo_elu_pll_configure(&disp_cc_pll2, regmap, &disp_cc_pll2_config);
1928
1929 /* Enable clock gating for MDP clocks */
1930 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1931
1932 /* Keep some clocks always-on */
1933 qcom_branch_set_clk_en(regmap, 0xe07c); /* DISP_CC_SLEEP_CLK */
1934 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
1935 qcom_branch_set_clk_en(regmap, 0xc00c); /* DISP_CC_MDSS_RSCC_AHB_CLK */
1936 qcom_branch_set_clk_en(regmap, 0xc008); /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
1937
1938 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8750_desc, regmap);
1939 if (ret)
1940 goto err_put_rpm;
1941
1942 pm_runtime_put(&pdev->dev);
1943
1944 return 0;
1945
1946err_put_rpm:
1947 pm_runtime_put_sync(&pdev->dev);
1948
1949 return ret;
1950}
1951
1952static struct platform_driver disp_cc_sm8750_driver = {
1953 .probe = disp_cc_sm8750_probe,
1954 .driver = {
1955 .name = "disp_cc-sm8750",
1956 .of_match_table = disp_cc_sm8750_match_table,
1957 },
1958};
1959
1960module_platform_driver(disp_cc_sm8750_driver);
1961
1962MODULE_DESCRIPTION("QTI DISPCC SM8750 Driver");
1963MODULE_LICENSE("GPL");