tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/platform_device.h>
8
9#include "clk-mtk.h"
10#include "clk-pll.h"
11
12#include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
13
14#define AP_PLL_CON_5 0x014
15#define ARMPLL_CON0 0x200
16#define ARMPLL_CON1 0x204
17#define ARMPLL_PWR_CON0 0x20c
18#define MAINPLL_CON0 0x210
19#define MAINPLL_CON1 0x214
20#define MAINPLL_PWR_CON0 0x21c
21#define UNIVPLL_CON0 0x220
22#define UNIVPLL_CON1 0x224
23#define UNIVPLL_PWR_CON0 0x22c
24#define MMPLL_CON0 0x230
25#define MMPLL_CON1 0x234
26#define MMPLL_PWR_CON0 0x23c
27#define MSDCPLL_CON0 0x240
28#define MSDCPLL_CON1 0x244
29#define MSDCPLL_PWR_CON0 0x24c
30#define VENCPLL_CON0 0x250
31#define VENCPLL_CON1 0x254
32#define VENCPLL_PWR_CON0 0x25c
33#define TVDPLL_CON0 0x260
34#define TVDPLL_CON1 0x264
35#define TVDPLL_PWR_CON0 0x26c
36#define APLL1_CON0 0x270
37#define APLL1_CON1 0x274
38#define APLL1_CON2 0x278
39#define APLL1_PWR_CON0 0x280
40#define APLL2_CON0 0x284
41#define APLL2_CON1 0x288
42#define APLL2_CON2 0x28c
43#define APLL2_PWR_CON0 0x294
44
45#define CON0_RST_BAR BIT(24)
46
47#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \
48 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
49 _tuner_en_bit, _pcw_reg, _pcwbits, _flags) { \
50 .id = _id, \
51 .name = _name, \
52 .parent_name = "clk26m", \
53 .reg = _reg, \
54 .pwr_reg = _pwr_reg, \
55 .en_mask = _en_mask, \
56 .rst_bar_mask = _rst_bar_mask, \
57 .pd_reg = _pd_reg, \
58 .pd_shift = _pd_shift, \
59 .tuner_reg = _tuner_reg, \
60 .tuner_en_reg = _tuner_en_reg, \
61 .tuner_en_bit = _tuner_en_bit, \
62 .pcw_reg = _pcw_reg, \
63 .pcw_chg_reg = _pcw_reg, \
64 .pcwbits = _pcwbits, \
65 .flags = _flags, \
66 }
67
68static const struct mtk_pll_data apmixedsys_plls[] = {
69 PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO),
70 PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_RST_BAR),
71 PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_RST_BAR),
72 PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
73 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 24, 0, 0, 0, MSDCPLL_CON1, 21, 0),
74 PLL(CLK_APMIXED_VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENCPLL_CON1, 24, 0, 0, 0, VENCPLL_CON1, 21, HAVE_RST_BAR),
75 PLL(CLK_APMIXED_TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0, 0, 0, TVDPLL_CON1, 21, 0),
76 PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CON2, AP_PLL_CON_5, 0, APLL1_CON1, 31, 0),
77 PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
78};
79
80static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
81{
82 void __iomem *base;
83 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84 struct clk_hw_onecell_data *clk_data;
85 int ret;
86
87 base = devm_ioremap_resource(&pdev->dev, res);
88 if (IS_ERR(base))
89 return PTR_ERR(base);
90
91 clk_data = mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(apmixedsys_plls));
92 if (!clk_data)
93 return -ENOMEM;
94 platform_set_drvdata(pdev, clk_data);
95
96 ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
97 ARRAY_SIZE(apmixedsys_plls), clk_data);
98 if (ret) {
99 dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
100 return ret;
101 }
102
103 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
104 clk_data);
105 if (ret)
106 dev_err(&pdev->dev,
107 "Failed to register clock provider: %d\n", ret);
108
109 return ret;
110}
111
112static void clk_mt6735_apmixed_remove(struct platform_device *pdev)
113{
114 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
115
116 mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
117}
118
119static const struct of_device_id of_match_mt6735_apmixedsys[] = {
120 { .compatible = "mediatek,mt6735-apmixedsys" },
121 { /* sentinel */ }
122};
123MODULE_DEVICE_TABLE(of, of_match_mt6735_apmixedsys);
124
125static struct platform_driver clk_mt6735_apmixedsys = {
126 .probe = clk_mt6735_apmixed_probe,
127 .remove = clk_mt6735_apmixed_remove,
128 .driver = {
129 .name = "clk-mt6735-apmixedsys",
130 .of_match_table = of_match_mt6735_apmixedsys,
131 },
132};
133module_platform_driver(clk_mt6735_apmixedsys);
134
135MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
136MODULE_DESCRIPTION("MediaTek MT6735 apmixedsys clock driver");
137MODULE_LICENSE("GPL");