Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Driver for Realtek RTS5139 USB card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Roger Tseng <rogerable@realtek.com>
8 */
9
10#ifndef __RTSX_USB_H
11#define __RTSX_USB_H
12
13#include <linux/usb.h>
14
15#define DRV_NAME_RTSX_USB "rtsx_usb"
16#define DRV_NAME_RTSX_USB_SDMMC "rtsx_usb_sdmmc"
17#define DRV_NAME_RTSX_USB_MS "rtsx_usb_ms"
18
19/* related module names */
20#define RTSX_USB_SD_CARD 0
21#define RTSX_USB_MS_CARD 1
22
23/* endpoint numbers */
24#define EP_BULK_OUT 1
25#define EP_BULK_IN 2
26#define EP_INTR_IN 3
27
28/* USB vendor requests */
29#define RTSX_USB_REQ_REG_OP 0x00
30#define RTSX_USB_REQ_POLL 0x02
31
32/* miscellaneous parameters */
33#define MIN_DIV_N 60
34#define MAX_DIV_N 120
35
36#define MAX_PHASE 15
37#define RX_TUNING_CNT 3
38
39#define QFN24 0
40#define LQFP48 1
41#define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
42
43/* data structures */
44struct rtsx_ucr {
45 u16 vendor_id;
46 u16 product_id;
47
48 int package;
49 u8 ic_version;
50 bool is_rts5179;
51
52 unsigned int cur_clk;
53
54 u8 *cmd_buf;
55 unsigned int cmd_idx;
56 u8 *rsp_buf;
57
58 struct usb_device *pusb_dev;
59 struct usb_interface *pusb_intf;
60 struct usb_sg_request current_sg;
61
62 struct timer_list sg_timer;
63 struct mutex dev_mutex;
64};
65
66/* buffer size */
67#define IOBUF_SIZE 1024
68
69/* prototypes of exported functions */
70extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
71
72extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
73extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
74 u8 data);
75
76extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
77 u8 data);
78extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
79 u8 *data);
80
81extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
82 u16 reg_addr, u8 mask, u8 data);
83extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
84extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
85extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
86 void *buf, unsigned int len, int use_sg,
87 unsigned int *act_len, int timeout);
88
89extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
90extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
91extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
92 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
93extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
94
95/* card status */
96#define SD_CD 0x01
97#define MS_CD 0x02
98#define XD_CD 0x04
99#define CD_MASK (SD_CD | MS_CD | XD_CD)
100#define SD_WP 0x08
101
102/* reader command field offset & parameters */
103#define READ_REG_CMD 0
104#define WRITE_REG_CMD 1
105#define CHECK_REG_CMD 2
106
107#define PACKET_TYPE 4
108#define CNT_H 5
109#define CNT_L 6
110#define STAGE_FLAG 7
111#define CMD_OFFSET 8
112#define SEQ_WRITE_DATA_OFFSET 12
113
114#define BATCH_CMD 0
115#define SEQ_READ 1
116#define SEQ_WRITE 2
117
118#define STAGE_R 0x01
119#define STAGE_DI 0x02
120#define STAGE_DO 0x04
121#define STAGE_MS_STATUS 0x08
122#define STAGE_XD_STATUS 0x10
123#define MODE_C 0x00
124#define MODE_CR (STAGE_R)
125#define MODE_CDIR (STAGE_R | STAGE_DI)
126#define MODE_CDOR (STAGE_R | STAGE_DO)
127
128#define EP0_OP_SHIFT 14
129#define EP0_READ_REG_CMD 2
130#define EP0_WRITE_REG_CMD 3
131
132#define rtsx_usb_cmd_hdr_tag(ucr) \
133 do { \
134 ucr->cmd_buf[0] = 'R'; \
135 ucr->cmd_buf[1] = 'T'; \
136 ucr->cmd_buf[2] = 'C'; \
137 ucr->cmd_buf[3] = 'R'; \
138 } while (0)
139
140static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
141{
142 rtsx_usb_cmd_hdr_tag(ucr);
143 ucr->cmd_idx = 0;
144 ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
145}
146
147/* internal register address */
148#define FPDCTL 0xFC00
149#define SSC_DIV_N_0 0xFC07
150#define SSC_CTL1 0xFC09
151#define SSC_CTL2 0xFC0A
152#define CFG_MODE 0xFC0E
153#define CFG_MODE_1 0xFC0F
154#define RCCTL 0xFC14
155#define SOF_WDOG 0xFC28
156#define SYS_DUMMY0 0xFC30
157
158#define MS_BLKEND 0xFD30
159#define MS_READ_START 0xFD31
160#define MS_READ_COUNT 0xFD32
161#define MS_WRITE_START 0xFD33
162#define MS_WRITE_COUNT 0xFD34
163#define MS_COMMAND 0xFD35
164#define MS_OLD_BLOCK_0 0xFD36
165#define MS_OLD_BLOCK_1 0xFD37
166#define MS_NEW_BLOCK_0 0xFD38
167#define MS_NEW_BLOCK_1 0xFD39
168#define MS_LOG_BLOCK_0 0xFD3A
169#define MS_LOG_BLOCK_1 0xFD3B
170#define MS_BUS_WIDTH 0xFD3C
171#define MS_PAGE_START 0xFD3D
172#define MS_PAGE_LENGTH 0xFD3E
173#define MS_CFG 0xFD40
174#define MS_TPC 0xFD41
175#define MS_TRANS_CFG 0xFD42
176#define MS_TRANSFER 0xFD43
177#define MS_INT_REG 0xFD44
178#define MS_BYTE_CNT 0xFD45
179#define MS_SECTOR_CNT_L 0xFD46
180#define MS_SECTOR_CNT_H 0xFD47
181#define MS_DBUS_H 0xFD48
182
183#define CARD_DMA1_CTL 0xFD5C
184#define CARD_PULL_CTL1 0xFD60
185#define CARD_PULL_CTL2 0xFD61
186#define CARD_PULL_CTL3 0xFD62
187#define CARD_PULL_CTL4 0xFD63
188#define CARD_PULL_CTL5 0xFD64
189#define CARD_PULL_CTL6 0xFD65
190#define CARD_EXIST 0xFD6F
191#define CARD_INT_PEND 0xFD71
192
193#define LDO_POWER_CFG 0xFD7B
194
195#define SD_CFG1 0xFDA0
196#define SD_CFG2 0xFDA1
197#define SD_CFG3 0xFDA2
198#define SD_STAT1 0xFDA3
199#define SD_STAT2 0xFDA4
200#define SD_BUS_STAT 0xFDA5
201#define SD_PAD_CTL 0xFDA6
202#define SD_SAMPLE_POINT_CTL 0xFDA7
203#define SD_PUSH_POINT_CTL 0xFDA8
204#define SD_CMD0 0xFDA9
205#define SD_CMD1 0xFDAA
206#define SD_CMD2 0xFDAB
207#define SD_CMD3 0xFDAC
208#define SD_CMD4 0xFDAD
209#define SD_CMD5 0xFDAE
210#define SD_BYTE_CNT_L 0xFDAF
211#define SD_BYTE_CNT_H 0xFDB0
212#define SD_BLOCK_CNT_L 0xFDB1
213#define SD_BLOCK_CNT_H 0xFDB2
214#define SD_TRANSFER 0xFDB3
215#define SD_CMD_STATE 0xFDB5
216#define SD_DATA_STATE 0xFDB6
217#define SD_VPCLK0_CTL 0xFC2A
218#define SD_VPCLK1_CTL 0xFC2B
219#define SD_DCMPS0_CTL 0xFC2C
220#define SD_DCMPS1_CTL 0xFC2D
221
222#define CARD_DMA1_CTL 0xFD5C
223
224#define HW_VERSION 0xFC01
225
226#define SSC_CLK_FPGA_SEL 0xFC02
227#define CLK_DIV 0xFC03
228#define SFSM_ED 0xFC04
229
230#define CD_DEGLITCH_WIDTH 0xFC20
231#define CD_DEGLITCH_EN 0xFC21
232#define AUTO_DELINK_EN 0xFC23
233
234#define FPGA_PULL_CTL 0xFC1D
235#define CARD_CLK_SOURCE 0xFC2E
236
237#define CARD_SHARE_MODE 0xFD51
238#define CARD_DRIVE_SEL 0xFD52
239#define CARD_STOP 0xFD53
240#define CARD_OE 0xFD54
241#define CARD_AUTO_BLINK 0xFD55
242#define CARD_GPIO 0xFD56
243#define SD30_DRIVE_SEL 0xFD57
244
245#define CARD_DATA_SOURCE 0xFD5D
246#define CARD_SELECT 0xFD5E
247
248#define CARD_CLK_EN 0xFD79
249#define CARD_PWR_CTL 0xFD7A
250
251#define OCPCTL 0xFD80
252#define OCPPARA1 0xFD81
253#define OCPPARA2 0xFD82
254#define OCPSTAT 0xFD83
255
256#define HS_USB_STAT 0xFE01
257#define HS_VCONTROL 0xFE26
258#define HS_VSTAIN 0xFE27
259#define HS_VLOADM 0xFE28
260#define HS_VSTAOUT 0xFE29
261
262#define MC_IRQ 0xFF00
263#define MC_IRQEN 0xFF01
264#define MC_FIFO_CTL 0xFF02
265#define MC_FIFO_BC0 0xFF03
266#define MC_FIFO_BC1 0xFF04
267#define MC_FIFO_STAT 0xFF05
268#define MC_FIFO_MODE 0xFF06
269#define MC_FIFO_RD_PTR0 0xFF07
270#define MC_FIFO_RD_PTR1 0xFF08
271#define MC_DMA_CTL 0xFF10
272#define MC_DMA_TC0 0xFF11
273#define MC_DMA_TC1 0xFF12
274#define MC_DMA_TC2 0xFF13
275#define MC_DMA_TC3 0xFF14
276#define MC_DMA_RST 0xFF15
277
278#define RBUF_SIZE_MASK 0xFBFF
279#define RBUF_BASE 0xF000
280#define PPBUF_BASE1 0xF800
281#define PPBUF_BASE2 0xFA00
282
283/* internal register value macros */
284#define POWER_OFF 0x03
285#define PARTIAL_POWER_ON 0x02
286#define POWER_ON 0x00
287#define POWER_MASK 0x03
288#define LDO3318_PWR_MASK 0x0C
289#define LDO_ON 0x00
290#define LDO_SUSPEND 0x08
291#define LDO_OFF 0x0C
292#define DV3318_AUTO_PWR_OFF 0x10
293#define FORCE_LDO_POWERB 0x60
294
295/* LDO_POWER_CFG */
296#define TUNE_SD18_MASK 0x1C
297#define TUNE_SD18_1V7 0x00
298#define TUNE_SD18_1V8 (0x01 << 2)
299#define TUNE_SD18_1V9 (0x02 << 2)
300#define TUNE_SD18_2V0 (0x03 << 2)
301#define TUNE_SD18_2V7 (0x04 << 2)
302#define TUNE_SD18_2V8 (0x05 << 2)
303#define TUNE_SD18_2V9 (0x06 << 2)
304#define TUNE_SD18_3V3 (0x07 << 2)
305
306/* CLK_DIV */
307#define CLK_CHANGE 0x80
308#define CLK_DIV_1 0x00
309#define CLK_DIV_2 0x01
310#define CLK_DIV_4 0x02
311#define CLK_DIV_8 0x03
312
313#define SSC_POWER_MASK 0x01
314#define SSC_POWER_DOWN 0x01
315#define SSC_POWER_ON 0x00
316
317#define FPGA_VER 0x80
318#define HW_VER_MASK 0x0F
319
320#define EXTEND_DMA1_ASYNC_SIGNAL 0x02
321
322/* CFG_MODE*/
323#define XTAL_FREE 0x80
324#define CLK_MODE_MASK 0x03
325#define CLK_MODE_12M_XTAL 0x00
326#define CLK_MODE_NON_XTAL 0x01
327#define CLK_MODE_24M_OSC 0x02
328#define CLK_MODE_48M_OSC 0x03
329
330/* CFG_MODE_1*/
331#define RTS5179 0x02
332
333#define NYET_EN 0x01
334#define NYET_MSAK 0x01
335
336#define SD30_DRIVE_MASK 0x07
337#define SD20_DRIVE_MASK 0x03
338
339#define DISABLE_SD_CD 0x08
340#define DISABLE_MS_CD 0x10
341#define DISABLE_XD_CD 0x20
342#define SD_CD_DEGLITCH_EN 0x01
343#define MS_CD_DEGLITCH_EN 0x02
344#define XD_CD_DEGLITCH_EN 0x04
345
346#define CARD_SHARE_LQFP48 0x04
347#define CARD_SHARE_QFN24 0x00
348#define CARD_SHARE_LQFP_SEL 0x04
349#define CARD_SHARE_XD 0x00
350#define CARD_SHARE_SD 0x01
351#define CARD_SHARE_MS 0x02
352#define CARD_SHARE_MASK 0x03
353
354
355/* SD30_DRIVE_SEL */
356#define DRIVER_TYPE_A 0x05
357#define DRIVER_TYPE_B 0x03
358#define DRIVER_TYPE_C 0x02
359#define DRIVER_TYPE_D 0x01
360
361/* SD_BUS_STAT */
362#define SD_CLK_TOGGLE_EN 0x80
363#define SD_CLK_FORCE_STOP 0x40
364#define SD_DAT3_STATUS 0x10
365#define SD_DAT2_STATUS 0x08
366#define SD_DAT1_STATUS 0x04
367#define SD_DAT0_STATUS 0x02
368#define SD_CMD_STATUS 0x01
369
370/* SD_PAD_CTL */
371#define SD_IO_USING_1V8 0x80
372#define SD_IO_USING_3V3 0x7F
373#define TYPE_A_DRIVING 0x00
374#define TYPE_B_DRIVING 0x01
375#define TYPE_C_DRIVING 0x02
376#define TYPE_D_DRIVING 0x03
377
378/* CARD_CLK_EN */
379#define SD_CLK_EN 0x04
380#define MS_CLK_EN 0x08
381
382/* CARD_SELECT */
383#define SD_MOD_SEL 2
384#define MS_MOD_SEL 3
385
386/* CARD_SHARE_MODE */
387#define CARD_SHARE_LQFP48 0x04
388#define CARD_SHARE_QFN24 0x00
389#define CARD_SHARE_LQFP_SEL 0x04
390#define CARD_SHARE_XD 0x00
391#define CARD_SHARE_SD 0x01
392#define CARD_SHARE_MS 0x02
393#define CARD_SHARE_MASK 0x03
394
395/* SSC_CTL1 */
396#define SSC_RSTB 0x80
397#define SSC_8X_EN 0x40
398#define SSC_FIX_FRAC 0x20
399#define SSC_SEL_1M 0x00
400#define SSC_SEL_2M 0x08
401#define SSC_SEL_4M 0x10
402#define SSC_SEL_8M 0x18
403
404/* SSC_CTL2 */
405#define SSC_DEPTH_MASK 0x03
406#define SSC_DEPTH_DISALBE 0x00
407#define SSC_DEPTH_2M 0x01
408#define SSC_DEPTH_1M 0x02
409#define SSC_DEPTH_512K 0x03
410
411/* SD_VPCLK0_CTL */
412#define PHASE_CHANGE 0x80
413#define PHASE_NOT_RESET 0x40
414
415/* SD_TRANSFER */
416#define SD_TRANSFER_START 0x80
417#define SD_TRANSFER_END 0x40
418#define SD_STAT_IDLE 0x20
419#define SD_TRANSFER_ERR 0x10
420#define SD_TM_NORMAL_WRITE 0x00
421#define SD_TM_AUTO_WRITE_3 0x01
422#define SD_TM_AUTO_WRITE_4 0x02
423#define SD_TM_AUTO_READ_3 0x05
424#define SD_TM_AUTO_READ_4 0x06
425#define SD_TM_CMD_RSP 0x08
426#define SD_TM_AUTO_WRITE_1 0x09
427#define SD_TM_AUTO_WRITE_2 0x0A
428#define SD_TM_NORMAL_READ 0x0C
429#define SD_TM_AUTO_READ_1 0x0D
430#define SD_TM_AUTO_READ_2 0x0E
431#define SD_TM_AUTO_TUNING 0x0F
432
433/* SD_CFG1 */
434#define SD_CLK_DIVIDE_0 0x00
435#define SD_CLK_DIVIDE_256 0xC0
436#define SD_CLK_DIVIDE_128 0x80
437#define SD_CLK_DIVIDE_MASK 0xC0
438#define SD_BUS_WIDTH_1BIT 0x00
439#define SD_BUS_WIDTH_4BIT 0x01
440#define SD_BUS_WIDTH_8BIT 0x02
441#define SD_ASYNC_FIFO_RST 0x10
442#define SD_20_MODE 0x00
443#define SD_DDR_MODE 0x04
444#define SD_30_MODE 0x08
445
446/* SD_CFG2 */
447#define SD_CALCULATE_CRC7 0x00
448#define SD_NO_CALCULATE_CRC7 0x80
449#define SD_CHECK_CRC16 0x00
450#define SD_NO_CHECK_CRC16 0x40
451#define SD_WAIT_CRC_TO_EN 0x20
452#define SD_WAIT_BUSY_END 0x08
453#define SD_NO_WAIT_BUSY_END 0x00
454#define SD_CHECK_CRC7 0x00
455#define SD_NO_CHECK_CRC7 0x04
456#define SD_RSP_LEN_0 0x00
457#define SD_RSP_LEN_6 0x01
458#define SD_RSP_LEN_17 0x02
459#define SD_RSP_TYPE_R0 0x04
460#define SD_RSP_TYPE_R1 0x01
461#define SD_RSP_TYPE_R1b 0x09
462#define SD_RSP_TYPE_R2 0x02
463#define SD_RSP_TYPE_R3 0x05
464#define SD_RSP_TYPE_R4 0x05
465#define SD_RSP_TYPE_R5 0x01
466#define SD_RSP_TYPE_R6 0x01
467#define SD_RSP_TYPE_R7 0x01
468
469/* SD_STAT1 */
470#define SD_CRC7_ERR 0x80
471#define SD_CRC16_ERR 0x40
472#define SD_CRC_WRITE_ERR 0x20
473#define SD_CRC_WRITE_ERR_MASK 0x1C
474#define GET_CRC_TIME_OUT 0x02
475#define SD_TUNING_COMPARE_ERR 0x01
476
477/* SD_DATA_STATE */
478#define SD_DATA_IDLE 0x80
479
480/* CARD_DATA_SOURCE */
481#define PINGPONG_BUFFER 0x01
482#define RING_BUFFER 0x00
483
484/* CARD_OE */
485#define SD_OUTPUT_EN 0x04
486#define MS_OUTPUT_EN 0x08
487
488/* CARD_STOP */
489#define SD_STOP 0x04
490#define MS_STOP 0x08
491#define SD_CLR_ERR 0x40
492#define MS_CLR_ERR 0x80
493
494/* CARD_CLK_SOURCE */
495#define CRC_FIX_CLK (0x00 << 0)
496#define CRC_VAR_CLK0 (0x01 << 0)
497#define CRC_VAR_CLK1 (0x02 << 0)
498#define SD30_FIX_CLK (0x00 << 2)
499#define SD30_VAR_CLK0 (0x01 << 2)
500#define SD30_VAR_CLK1 (0x02 << 2)
501#define SAMPLE_FIX_CLK (0x00 << 4)
502#define SAMPLE_VAR_CLK0 (0x01 << 4)
503#define SAMPLE_VAR_CLK1 (0x02 << 4)
504
505/* SD_SAMPLE_POINT_CTL */
506#define DDR_FIX_RX_DAT 0x00
507#define DDR_VAR_RX_DAT 0x80
508#define DDR_FIX_RX_DAT_EDGE 0x00
509#define DDR_FIX_RX_DAT_14_DELAY 0x40
510#define DDR_FIX_RX_CMD 0x00
511#define DDR_VAR_RX_CMD 0x20
512#define DDR_FIX_RX_CMD_POS_EDGE 0x00
513#define DDR_FIX_RX_CMD_14_DELAY 0x10
514#define SD20_RX_POS_EDGE 0x00
515#define SD20_RX_14_DELAY 0x08
516#define SD20_RX_SEL_MASK 0x08
517
518/* SD_PUSH_POINT_CTL */
519#define DDR_FIX_TX_CMD_DAT 0x00
520#define DDR_VAR_TX_CMD_DAT 0x80
521#define DDR_FIX_TX_DAT_14_TSU 0x00
522#define DDR_FIX_TX_DAT_12_TSU 0x40
523#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
524#define DDR_FIX_TX_CMD_14_AHEAD 0x20
525#define SD20_TX_NEG_EDGE 0x00
526#define SD20_TX_14_AHEAD 0x10
527#define SD20_TX_SEL_MASK 0x10
528#define DDR_VAR_SDCLK_POL_SWAP 0x01
529
530/* MS_CFG */
531#define SAMPLE_TIME_RISING 0x00
532#define SAMPLE_TIME_FALLING 0x80
533#define PUSH_TIME_DEFAULT 0x00
534#define PUSH_TIME_ODD 0x40
535#define NO_EXTEND_TOGGLE 0x00
536#define EXTEND_TOGGLE_CHK 0x20
537#define MS_BUS_WIDTH_1 0x00
538#define MS_BUS_WIDTH_4 0x10
539#define MS_BUS_WIDTH_8 0x18
540#define MS_2K_SECTOR_MODE 0x04
541#define MS_512_SECTOR_MODE 0x00
542#define MS_TOGGLE_TIMEOUT_EN 0x00
543#define MS_TOGGLE_TIMEOUT_DISEN 0x01
544#define MS_NO_CHECK_INT 0x02
545
546/* MS_TRANS_CFG */
547#define WAIT_INT 0x80
548#define NO_WAIT_INT 0x00
549#define NO_AUTO_READ_INT_REG 0x00
550#define AUTO_READ_INT_REG 0x40
551#define MS_CRC16_ERR 0x20
552#define MS_RDY_TIMEOUT 0x10
553#define MS_INT_CMDNK 0x08
554#define MS_INT_BREQ 0x04
555#define MS_INT_ERR 0x02
556#define MS_INT_CED 0x01
557
558/* MS_TRANSFER */
559#define MS_TRANSFER_START 0x80
560#define MS_TRANSFER_END 0x40
561#define MS_TRANSFER_ERR 0x20
562#define MS_BS_STATE 0x10
563#define MS_TM_READ_BYTES 0x00
564#define MS_TM_NORMAL_READ 0x01
565#define MS_TM_WRITE_BYTES 0x04
566#define MS_TM_NORMAL_WRITE 0x05
567#define MS_TM_AUTO_READ 0x08
568#define MS_TM_AUTO_WRITE 0x0C
569#define MS_TM_SET_CMD 0x06
570#define MS_TM_COPY_PAGE 0x07
571#define MS_TM_MULTI_READ 0x02
572#define MS_TM_MULTI_WRITE 0x03
573
574/* MC_FIFO_CTL */
575#define FIFO_FLUSH 0x01
576
577/* MC_DMA_RST */
578#define DMA_RESET 0x01
579
580/* MC_DMA_CTL */
581#define DMA_TC_EQ_0 0x80
582#define DMA_DIR_TO_CARD 0x00
583#define DMA_DIR_FROM_CARD 0x02
584#define DMA_EN 0x01
585#define DMA_128 (0 << 2)
586#define DMA_256 (1 << 2)
587#define DMA_512 (2 << 2)
588#define DMA_1024 (3 << 2)
589#define DMA_PACK_SIZE_MASK 0x0C
590
591/* CARD_INT_PEND */
592#define XD_INT 0x10
593#define MS_INT 0x08
594#define SD_INT 0x04
595
596/* LED operations*/
597static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
598{
599 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
600}
601
602static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
603{
604 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
605}
606
607/* HW error clearing */
608static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
609{
610 rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
611}
612
613static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
614{
615 rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
616 FIFO_FLUSH, FIFO_FLUSH);
617 rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
618}
619#endif /* __RTS51139_H */