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Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_HW_BTRS_LNL_REG_H__
7#define __IVPU_HW_BTRS_LNL_REG_H__
8
9#include <linux/bits.h>
10
11#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u
12#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
13#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
14#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
15#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
16#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
17#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
18#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
19
20#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK 0x00000004u
21#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK 0x00000008u
22
23#define VPU_HW_BTRS_LNL_HM_ATS 0x0000000cu
24
25#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 0x00000010u
26#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 0x00000014u
27#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR 0x00000018u
28
29#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG 0x0000001cu
30#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR 0x00000020u
31
32#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
33
34#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG 0x00000040u
35#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR 0x00000044u
36
37#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW 0x00000048u
38#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH 0x0000004cu
39#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR 0x00000050u
40
41#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS 0x00000054u
42
43#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW 0x00000058u
44#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH 0x0000005cu
45#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR 0x00000060u
46
47#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS 0x00000070u
48#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK GENMASK(7, 0)
49#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK GENMASK(15, 8)
50#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK GENMASK(23, 16)
51#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK GENMASK(31, 24)
52
53#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW 0x00000074u
54#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0)
55#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8)
56#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16)
57#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24)
58
59#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 0x00000130u
60#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
61#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
62
63#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 0x00000134u
64#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
65#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
66
67#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 0x00000138u
68#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
69#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
70
71#define VPU_HW_BTRS_LNL_WP_REQ_CMD 0x0000013cu
72#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
73
74#define VPU_HW_BTRS_LNL_PLL_FREQ 0x00000148u
75#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
76
77#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u
78#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0)
79#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
80
81#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
82#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)
83#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
84#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
85#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
86#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
87#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
88#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
89
90#define VPU_HW_BTRS_LNL_IP_RESET 0x00000160u
91#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK BIT_MASK(0)
92
93#define VPU_HW_BTRS_LNL_D0I3_CONTROL 0x00000164u
94#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
95#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK BIT_MASK(2)
96
97#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET 0x00000168u
98#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE 0x0000016cu
99#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE 0x00000170u
100
101#define VPU_HW_BTRS_LNL_FMIN_FUSE 0x00000174u
102#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
103#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
104
105#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u
106#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
107
108#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */