tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Linaro Ltd.
4 */
5
6#include "ste-nomadik-pinctrl.dtsi"
7
8&pinctrl {
9 /* Settings for all UART default and sleep states */
10 uart0 {
11 u0_a_1_default: u0_a_1_default {
12 default_mux {
13 function = "u0";
14 groups = "u0_a_1";
15 };
16 default_cfg1 {
17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
18 ste,config = <&in_pu>;
19 };
20 default_cfg2 {
21 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
22 ste,config = <&out_hi>;
23 };
24 };
25
26 u0_a_1_sleep: u0_a_1_sleep {
27 sleep_cfg1 {
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
29 ste,config = <&slpm_in_wkup_pdis>;
30 };
31 sleep_cfg2 {
32 pins = "GPIO1_AJ3"; /* RTS */
33 ste,config = <&slpm_out_hi_wkup_pdis>;
34 };
35 sleep_cfg3 {
36 pins = "GPIO3_AH3"; /* TXD */
37 ste,config = <&slpm_out_wkup_pdis>;
38 };
39 };
40 };
41
42 uart1 {
43 u1rxtx_a_1_default: u1rxtx_a_1_default {
44 default_mux {
45 function = "u1";
46 groups = "u1rxtx_a_1";
47 };
48 default_cfg1 {
49 pins = "GPIO4_AH6"; /* RXD */
50 ste,config = <&in_pu>;
51 };
52 default_cfg2 {
53 pins = "GPIO5_AG6"; /* TXD */
54 ste,config = <&out_hi>;
55 };
56 };
57
58 u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
59 sleep_cfg1 {
60 pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&slpm_in_wkup_pdis>;
62 };
63 sleep_cfg2 {
64 pins = "GPIO5_AG6"; /* TXD */
65 ste,config = <&slpm_out_wkup_pdis>;
66 };
67 };
68
69 u1ctsrts_a_1_default: u1ctsrts_a_1_default {
70 default_mux {
71 function = "u1";
72 groups = "u1ctsrts_a_1";
73 };
74 default_cfg1 {
75 pins = "GPIO6_AF6"; /* CTS */
76 ste,config = <&in_pu>;
77 };
78 default_cfg2 {
79 pins = "GPIO7_AG5"; /* RTS */
80 ste,config = <&out_hi>;
81 };
82 };
83
84 u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
85 sleep_cfg1 {
86 pins = "GPIO6_AF6"; /* CTS */
87 ste,config = <&slpm_in_wkup_pdis>;
88 };
89 sleep_cfg2 {
90 pins = "GPIO7_AG5"; /* RTS */
91 ste,config = <&slpm_out_hi_wkup_pdis>;
92 };
93 };
94 };
95
96 uart2 {
97 u2rxtx_c_1_default: u2rxtx_c_1_default {
98 default_mux {
99 function = "u2";
100 groups = "u2rxtx_c_1";
101 };
102 default_cfg1 {
103 pins = "GPIO29_W2"; /* RXD */
104 ste,config = <&in_pu>;
105 };
106 default_cfg2 {
107 pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_hi>;
109 };
110 };
111
112 u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
113 sleep_cfg1 {
114 pins = "GPIO29_W2"; /* RXD */
115 ste,config = <&in_wkup_pdis>;
116 };
117 sleep_cfg2 {
118 pins = "GPIO30_W3"; /* TXD */
119 ste,config = <&out_wkup_pdis>;
120 };
121 };
122 };
123
124 /* Settings for all I2C default and sleep states */
125 i2c0 {
126 i2c0_a_1_default: i2c0_a_1_default {
127 default_mux {
128 function = "i2c0";
129 groups = "i2c0_a_1";
130 };
131 default_cfg1 {
132 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
133 ste,config = <&in_nopull>;
134 };
135 };
136
137 i2c0_a_1_sleep: i2c0_a_1_sleep {
138 sleep_cfg1 {
139 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
140 ste,config = <&slpm_in_wkup_pdis>;
141 };
142 };
143 };
144
145 i2c1 {
146 i2c1_b_2_default: i2c1_b_2_default {
147 default_mux {
148 function = "i2c1";
149 groups = "i2c1_b_2";
150 };
151 default_cfg1 {
152 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
153 ste,config = <&in_nopull>;
154 };
155 };
156
157 i2c1_b_2_sleep: i2c1_b_2_sleep {
158 sleep_cfg1 {
159 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
160 ste,config = <&slpm_in_wkup_pdis>;
161 };
162 };
163 };
164
165 i2c2 {
166 i2c2_b_1_default: i2c2_b_1_default {
167 default_mux {
168 function = "i2c2";
169 groups = "i2c2_b_1";
170 };
171 default_cfg1 {
172 pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
173 ste,config = <&in_nopull>;
174 };
175 };
176
177 i2c2_b_1_sleep: i2c2_b_1_sleep {
178 sleep_cfg1 {
179 pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
180 ste,config = <&slpm_in_wkup_pdis>;
181 };
182 };
183
184 i2c2_b_2_default: i2c2_b_2_default {
185 default_mux {
186 function = "i2c2";
187 groups = "i2c2_b_2";
188 };
189 default_cfg1 {
190 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
191 ste,config = <&in_nopull>;
192 };
193 };
194
195 i2c2_b_2_sleep: i2c2_b_2_sleep {
196 sleep_cfg1 {
197 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
198 ste,config = <&slpm_in_wkup_pdis>;
199 };
200 };
201 };
202
203 i2c3 {
204 i2c3_c_2_default: i2c3_c_2_default {
205 default_mux {
206 function = "i2c3";
207 groups = "i2c3_c_2";
208 };
209 default_cfg1 {
210 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
211 ste,config = <&in_nopull>;
212 };
213 };
214
215 i2c3_c_2_sleep: i2c3_c_2_sleep {
216 sleep_cfg1 {
217 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
218 ste,config = <&slpm_in_wkup_pdis>;
219 };
220 };
221 };
222
223 /*
224 * Activating I2C4 will conflict with UART1 about the same pins so do not
225 * enable I2C4 and UART1 at the same time.
226 */
227 i2c4 {
228 i2c4_b_1_default: i2c4_b_1_default {
229 default_mux {
230 function = "i2c4";
231 groups = "i2c4_b_1";
232 };
233 default_cfg1 {
234 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
235 ste,config = <&in_nopull>;
236 };
237 };
238
239 i2c4_b_1_sleep: i2c4_b_1_sleep {
240 sleep_cfg1 {
241 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
242 ste,config = <&slpm_in_wkup_pdis>;
243 };
244 };
245 };
246
247 /* Settings for all MMC/SD/SDIO default and sleep states */
248 sdi0 {
249 /* This is the external SD card slot, 4 bits wide */
250 mc0_a_1_default: mc0_a_1_default {
251 default_mux {
252 function = "mc0";
253 groups = "mc0_a_1";
254 };
255 default_cfg1 {
256 pins =
257 "GPIO18_AC2", /* CMDDIR */
258 "GPIO19_AC1", /* DAT0DIR */
259 "GPIO20_AB4"; /* DAT2DIR */
260 ste,config = <&out_hi>;
261 };
262 default_cfg2 {
263 pins = "GPIO22_AA3"; /* FBCLK */
264 ste,config = <&in_nopull>;
265 };
266 default_cfg3 {
267 pins = "GPIO23_AA4"; /* CLK */
268 ste,config = <&out_lo>;
269 };
270 default_cfg4 {
271 pins =
272 "GPIO24_AB2", /* CMD */
273 "GPIO25_Y4", /* DAT0 */
274 "GPIO26_Y2", /* DAT1 */
275 "GPIO27_AA2", /* DAT2 */
276 "GPIO28_AA1"; /* DAT3 */
277 ste,config = <&in_pu>;
278 };
279 };
280
281 mc0_a_1_sleep: mc0_a_1_sleep {
282 sleep_cfg1 {
283 pins =
284 "GPIO18_AC2", /* CMDDIR */
285 "GPIO19_AC1", /* DAT0DIR */
286 "GPIO20_AB4"; /* DAT2DIR */
287 ste,config = <&slpm_out_hi_wkup_pdis>;
288 };
289 sleep_cfg2 {
290 pins =
291 "GPIO22_AA3", /* FBCLK */
292 "GPIO24_AB2", /* CMD */
293 "GPIO25_Y4", /* DAT0 */
294 "GPIO26_Y2", /* DAT1 */
295 "GPIO27_AA2", /* DAT2 */
296 "GPIO28_AA1"; /* DAT3 */
297 ste,config = <&slpm_in_wkup_pdis>;
298 };
299 sleep_cfg3 {
300 pins = "GPIO23_AA4"; /* CLK */
301 ste,config = <&slpm_out_lo_wkup_pdis>;
302 };
303 };
304
305 mc0_a_2_default: mc0_a_2_default {
306 default_mux {
307 function = "mc0";
308 groups = "mc0_a_2";
309 };
310 default_cfg1 {
311 pins = "GPIO22_AA3"; /* FBCLK */
312 ste,config = <&in_nopull>;
313 };
314 default_cfg2 {
315 pins = "GPIO23_AA4"; /* CLK */
316 ste,config = <&out_lo>;
317 };
318 default_cfg3 {
319 pins =
320 "GPIO24_AB2", /* CMD */
321 "GPIO25_Y4", /* DAT0 */
322 "GPIO26_Y2", /* DAT1 */
323 "GPIO27_AA2", /* DAT2 */
324 "GPIO28_AA1"; /* DAT3 */
325 ste,config = <&in_pu>;
326 };
327 };
328
329 mc0_a_2_sleep: mc0_a_2_sleep {
330 sleep_cfg1 {
331 pins =
332 "GPIO22_AA3", /* FBCLK */
333 "GPIO24_AB2", /* CMD */
334 "GPIO25_Y4", /* DAT0 */
335 "GPIO26_Y2", /* DAT1 */
336 "GPIO27_AA2", /* DAT2 */
337 "GPIO28_AA1"; /* DAT3 */
338 ste,config = <&slpm_in_wkup_pdis>;
339 };
340 sleep_cfg2 {
341 pins = "GPIO23_AA4"; /* CLK */
342 ste,config = <&slpm_out_lo_wkup_pdis>;
343 };
344 };
345 };
346
347 sdi1 {
348 /* This is the WLAN SDIO 4 bits wide */
349 mc1_a_1_default: mc1_a_1_default {
350 default_mux {
351 function = "mc1";
352 groups = "mc1_a_1";
353 };
354 default_cfg1 {
355 pins = "GPIO208_AH16"; /* CLK */
356 ste,config = <&out_lo>;
357 };
358 default_cfg2 {
359 pins = "GPIO209_AG15"; /* FBCLK */
360 ste,config = <&in_nopull>;
361 };
362 default_cfg3 {
363 pins =
364 "GPIO210_AJ15", /* CMD */
365 "GPIO211_AG14", /* DAT0 */
366 "GPIO212_AF13", /* DAT1 */
367 "GPIO213_AG13", /* DAT2 */
368 "GPIO214_AH15"; /* DAT3 */
369 ste,config = <&in_pu>;
370 };
371 };
372
373 mc1_a_1_sleep: mc1_a_1_sleep {
374 sleep_cfg1 {
375 pins = "GPIO208_AH16"; /* CLK */
376 ste,config = <&slpm_out_lo_wkup_pdis>;
377 };
378 sleep_cfg2 {
379 pins =
380 "GPIO209_AG15", /* FBCLK */
381 "GPIO210_AJ15", /* CMD */
382 "GPIO211_AG14", /* DAT0 */
383 "GPIO212_AF13", /* DAT1 */
384 "GPIO213_AG13", /* DAT2 */
385 "GPIO214_AH15"; /* DAT3 */
386 ste,config = <&slpm_in_wkup_pdis>;
387 };
388 };
389
390 mc1_a_2_default: mc1_a_2_default {
391 default_mux {
392 function = "mc1";
393 groups = "mc1_a_2";
394 };
395 default_cfg1 {
396 pins = "GPIO208_AH16"; /* CLK */
397 ste,config = <&out_lo>;
398 };
399 default_cfg2 {
400 pins =
401 "GPIO210_AJ15", /* CMD */
402 "GPIO211_AG14", /* DAT0 */
403 "GPIO212_AF13", /* DAT1 */
404 "GPIO213_AG13", /* DAT2 */
405 "GPIO214_AH15"; /* DAT3 */
406 ste,config = <&in_pu>;
407 };
408 };
409
410 mc1_a_2_sleep: mc1_a_2_sleep {
411 sleep_cfg1 {
412 pins = "GPIO208_AH16"; /* CLK */
413 ste,config = <&slpm_out_lo_wkup_pdis>;
414 };
415 sleep_cfg2 {
416 pins =
417 "GPIO210_AJ15", /* CMD */
418 "GPIO211_AG14", /* DAT0 */
419 "GPIO212_AF13", /* DAT1 */
420 "GPIO213_AG13", /* DAT2 */
421 "GPIO214_AH15"; /* DAT3 */
422 ste,config = <&slpm_in_wkup_pdis>;
423 };
424 };
425 };
426
427 sdi2 {
428 /* This is the eMMC 8 bits wide, usually PoP eMMC */
429 mc2_a_1_default: mc2_a_1_default {
430 default_mux {
431 function = "mc2";
432 groups = "mc2_a_1";
433 };
434 default_cfg1 {
435 pins = "GPIO128_A5"; /* CLK */
436 ste,config = <&out_lo>;
437 };
438 default_cfg2 {
439 pins = "GPIO130_C8"; /* FBCLK */
440 ste,config = <&in_nopull>;
441 };
442 default_cfg3 {
443 pins =
444 "GPIO129_B4", /* CMD */
445 "GPIO131_A12", /* DAT0 */
446 "GPIO132_C10", /* DAT1 */
447 "GPIO133_B10", /* DAT2 */
448 "GPIO134_B9", /* DAT3 */
449 "GPIO135_A9", /* DAT4 */
450 "GPIO136_C7", /* DAT5 */
451 "GPIO137_A7", /* DAT6 */
452 "GPIO138_C5"; /* DAT7 */
453 ste,config = <&in_pu>;
454 };
455 };
456
457 /* MC2 without feedback clock on A8 */
458 mc2_a_2_default: mc2_a_2_default {
459 default_mux {
460 function = "mc2";
461 groups = "mc2_a_2";
462 };
463 default_cfg1 {
464 pins = "GPIO128_A5"; /* CLK */
465 ste,config = <&out_lo>;
466 };
467 default_cfg2 {
468 pins =
469 "GPIO129_B4", /* CMD */
470 "GPIO131_A12", /* DAT0 */
471 "GPIO132_C10", /* DAT1 */
472 "GPIO133_B10", /* DAT2 */
473 "GPIO134_B9", /* DAT3 */
474 "GPIO135_A9", /* DAT4 */
475 "GPIO136_C7", /* DAT5 */
476 "GPIO137_A7", /* DAT6 */
477 "GPIO138_C5"; /* DAT7 */
478 ste,config = <&in_pu>;
479 };
480 };
481
482 mc2_a_1_sleep: mc2_a_1_sleep {
483 sleep_cfg1 {
484 pins = "GPIO128_A5"; /* CLK */
485 ste,config = <&out_lo_wkup_pdis>;
486 };
487 sleep_cfg2 {
488 pins =
489 "GPIO130_C8", /* FBCLK */
490 "GPIO129_B4"; /* CMD */
491 ste,config = <&in_wkup_pdis_en>;
492 };
493 sleep_cfg3 {
494 pins =
495 "GPIO131_A12", /* DAT0 */
496 "GPIO132_C10", /* DAT1 */
497 "GPIO133_B10", /* DAT2 */
498 "GPIO134_B9", /* DAT3 */
499 "GPIO135_A9", /* DAT4 */
500 "GPIO136_C7", /* DAT5 */
501 "GPIO137_A7", /* DAT6 */
502 "GPIO138_C5"; /* DAT7 */
503 ste,config = <&in_wkup_pdis>;
504 };
505 };
506
507 mc2_a_2_sleep: mc2_a_2_sleep {
508 sleep_cfg1 {
509 pins = "GPIO128_A5"; /* CLK */
510 ste,config = <&out_lo_wkup_pdis>;
511 };
512 sleep_cfg2 {
513 pins =
514 "GPIO129_B4"; /* CMD */
515 ste,config = <&in_wkup_pdis_en>;
516 };
517 sleep_cfg3 {
518 pins =
519 "GPIO131_A12", /* DAT0 */
520 "GPIO132_C10", /* DAT1 */
521 "GPIO133_B10", /* DAT2 */
522 "GPIO134_B9", /* DAT3 */
523 "GPIO135_A9", /* DAT4 */
524 "GPIO136_C7", /* DAT5 */
525 "GPIO137_A7", /* DAT6 */
526 "GPIO138_C5"; /* DAT7 */
527 ste,config = <&in_wkup_pdis>;
528 };
529 };
530 };
531
532 sdi4 {
533 /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
534 mc4_a_1_default: mc4_a_1_default {
535 default_mux {
536 function = "mc4";
537 groups = "mc4_a_1";
538 };
539 default_cfg1 {
540 pins = "GPIO203_AE23"; /* CLK */
541 ste,config = <&out_lo>;
542 };
543 default_cfg2 {
544 pins = "GPIO202_AF25"; /* FBCLK */
545 ste,config = <&in_nopull>;
546 };
547 default_cfg3 {
548 pins =
549 "GPIO201_AF24", /* CMD */
550 "GPIO200_AH26", /* DAT0 */
551 "GPIO199_AH23", /* DAT1 */
552 "GPIO198_AG25", /* DAT2 */
553 "GPIO197_AH24", /* DAT3 */
554 "GPIO207_AJ23", /* DAT4 */
555 "GPIO206_AG24", /* DAT5 */
556 "GPIO205_AG23", /* DAT6 */
557 "GPIO204_AF23"; /* DAT7 */
558 ste,config = <&in_pu>;
559 };
560 };
561
562 mc4_a_1_sleep: mc4_a_1_sleep {
563 sleep_cfg1 {
564 pins = "GPIO203_AE23"; /* CLK */
565 ste,config = <&out_lo_wkup_pdis>;
566 };
567 sleep_cfg2 {
568 pins =
569 "GPIO202_AF25", /* FBCLK */
570 "GPIO201_AF24", /* CMD */
571 "GPIO200_AH26", /* DAT0 */
572 "GPIO199_AH23", /* DAT1 */
573 "GPIO198_AG25", /* DAT2 */
574 "GPIO197_AH24", /* DAT3 */
575 "GPIO207_AJ23", /* DAT4 */
576 "GPIO206_AG24", /* DAT5 */
577 "GPIO205_AG23", /* DAT6 */
578 "GPIO204_AF23"; /* DAT7 */
579 ste,config = <&slpm_in_wkup_pdis>;
580 };
581 };
582 };
583
584 /*
585 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
586 * cannot be muxed onto any pins.
587 */
588 msp0 {
589 msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
590 default_msp0_mux {
591 function = "msp0";
592 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
593 };
594 default_msp0_cfg {
595 pins =
596 "GPIO12_AC4", /* TXD */
597 "GPIO15_AC3", /* RXD */
598 "GPIO13_AF3", /* TFS */
599 "GPIO14_AE3"; /* TCK */
600 ste,config = <&in_nopull>;
601 };
602 };
603 };
604
605 msp1 {
606 msp1txrx_a_1_default: msp1txrx_a_1_default {
607 default_mux {
608 function = "msp1";
609 groups = "msp1txrx_a_1", "msp1_a_1";
610 };
611 default_cfg1 {
612 pins = "GPIO33_AF2";
613 ste,config = <&out_lo>;
614 };
615 default_cfg2 {
616 pins =
617 "GPIO34_AE1",
618 "GPIO35_AE2",
619 "GPIO36_AG2";
620 ste,config = <&in_nopull>;
621 };
622 };
623 };
624
625 msp2 {
626 msp2_a_1_default: msp2_a_1_default {
627 /* MSP2 usually used for HDMI audio */
628 default_mux {
629 function = "msp2";
630 groups = "msp2_a_1";
631 };
632 default_cfg1 {
633 pins =
634 "GPIO193_AH27", /* TXD */
635 "GPIO194_AF27", /* TCK */
636 "GPIO195_AG28"; /* TFS */
637 ste,config = <&in_pd>;
638 };
639 default_cfg2 {
640 pins = "GPIO196_AG26"; /* RXD */
641 ste,config = <&out_lo>;
642 };
643 };
644 };
645
646 musb {
647 usb_a_1_default: usb_a_1_default {
648 default_mux {
649 function = "usb";
650 groups = "usb_a_1";
651 };
652 default_cfg1 {
653 pins =
654 "GPIO256_AF28", /* NXT */
655 "GPIO258_AD29", /* XCLK */
656 "GPIO259_AC29", /* DIR */
657 "GPIO260_AD28", /* DAT7 */
658 "GPIO261_AD26", /* DAT6 */
659 "GPIO262_AE26", /* DAT5 */
660 "GPIO263_AG29", /* DAT4 */
661 "GPIO264_AE27", /* DAT3 */
662 "GPIO265_AD27", /* DAT2 */
663 "GPIO266_AC28", /* DAT1 */
664 "GPIO267_AC27"; /* DAT0 */
665 ste,config = <&in_nopull>;
666 };
667 default_cfg2 {
668 pins = "GPIO257_AE29"; /* STP */
669 ste,config = <&out_hi>;
670 };
671 };
672
673 usb_a_1_sleep: usb_a_1_sleep {
674 sleep_cfg1 {
675 pins =
676 "GPIO256_AF28", /* NXT */
677 "GPIO258_AD29", /* XCLK */
678 "GPIO259_AC29"; /* DIR */
679 ste,config = <&slpm_wkup_pdis_en>;
680 };
681 sleep_cfg2 {
682 pins = "GPIO257_AE29"; /* STP */
683 ste,config = <&slpm_out_hi_wkup_pdis>;
684 };
685 sleep_cfg3 {
686 pins =
687 "GPIO260_AD28", /* DAT7 */
688 "GPIO261_AD26", /* DAT6 */
689 "GPIO262_AE26", /* DAT5 */
690 "GPIO263_AG29", /* DAT4 */
691 "GPIO264_AE27", /* DAT3 */
692 "GPIO265_AD27", /* DAT2 */
693 "GPIO266_AC28", /* DAT1 */
694 "GPIO267_AC27"; /* DAT0 */
695 ste,config = <&slpm_in_wkup_pdis_en>;
696 };
697 };
698 };
699};