tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
12
13description:
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15 have dual GMAC ports.
16
17properties:
18 compatible:
19 enum:
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
29
30 reg:
31 maxItems: 1
32
33 clocks:
34 minItems: 2
35 maxItems: 24
36
37 clock-names:
38 minItems: 2
39 maxItems: 24
40
41 interrupts:
42 minItems: 1
43 maxItems: 4
44
45 power-domains:
46 maxItems: 1
47
48 resets:
49 maxItems: 3
50
51 reset-names:
52 items:
53 - const: fe
54 - const: gmac
55 - const: ppe
56
57 mediatek,ethsys:
58 $ref: /schemas/types.yaml#/definitions/phandle
59 description:
60 Phandle to the syscon node that handles the port setup.
61
62 cci-control-port: true
63
64 mediatek,hifsys:
65 $ref: /schemas/types.yaml#/definitions/phandle
66 description:
67 Phandle to the mediatek hifsys controller used to provide various clocks
68 and reset to the system.
69
70 mediatek,infracfg:
71 $ref: /schemas/types.yaml#/definitions/phandle
72 description:
73 Phandle to the syscon node that handles the path from GMAC to
74 PHY variants.
75
76 mediatek,pcie-mirror:
77 $ref: /schemas/types.yaml#/definitions/phandle
78 description:
79 Phandle to the mediatek pcie-mirror controller.
80
81 mediatek,pctl:
82 $ref: /schemas/types.yaml#/definitions/phandle
83 description:
84 Phandle to the syscon node that handles the ports slew rate and
85 driver current.
86
87 mediatek,sgmiisys:
88 $ref: /schemas/types.yaml#/definitions/phandle-array
89 minItems: 1
90 maxItems: 2
91 items:
92 maxItems: 1
93 description:
94 A list of phandle to the syscon node that handles the SGMII setup which is required for
95 those SoCs equipped with SGMII.
96
97 mediatek,wed:
98 $ref: /schemas/types.yaml#/definitions/phandle-array
99 minItems: 2
100 maxItems: 2
101 items:
102 maxItems: 1
103 description:
104 List of phandles to wireless ethernet dispatch nodes.
105
106 mediatek,wed-pcie:
107 $ref: /schemas/types.yaml#/definitions/phandle
108 description:
109 Phandle to the mediatek wed-pcie controller.
110
111 dma-coherent: true
112
113 mdio-bus:
114 $ref: mdio.yaml#
115 unevaluatedProperties: false
116
117 "#address-cells":
118 const: 1
119
120 "#size-cells":
121 const: 0
122
123allOf:
124 - $ref: ethernet-controller.yaml#
125 - if:
126 properties:
127 compatible:
128 contains:
129 enum:
130 - mediatek,mt2701-eth
131 - mediatek,mt7623-eth
132 then:
133 properties:
134 interrupts:
135 minItems: 3
136 maxItems: 3
137
138 clocks:
139 minItems: 4
140 maxItems: 4
141
142 clock-names:
143 items:
144 - const: ethif
145 - const: esw
146 - const: gp1
147 - const: gp2
148
149 mediatek,infracfg: false
150
151 mediatek,wed: false
152
153 mediatek,wed-pcie: false
154 else:
155 properties:
156 mediatek,pctl: false
157
158 - if:
159 properties:
160 compatible:
161 contains:
162 enum:
163 - mediatek,mt7621-eth
164 then:
165 properties:
166 interrupts:
167 maxItems: 1
168
169 clocks:
170 minItems: 2
171 maxItems: 2
172
173 clock-names:
174 items:
175 - const: ethif
176 - const: fe
177
178 mediatek,infracfg: false
179
180 mediatek,wed: false
181
182 mediatek,wed-pcie: false
183
184 - if:
185 properties:
186 compatible:
187 contains:
188 const: mediatek,mt7622-eth
189 then:
190 properties:
191 interrupts:
192 minItems: 3
193 maxItems: 3
194
195 clocks:
196 minItems: 11
197 maxItems: 11
198
199 clock-names:
200 items:
201 - const: ethif
202 - const: esw
203 - const: gp0
204 - const: gp1
205 - const: gp2
206 - const: sgmii_tx250m
207 - const: sgmii_rx250m
208 - const: sgmii_cdr_ref
209 - const: sgmii_cdr_fb
210 - const: sgmii_ck
211 - const: eth2pll
212
213 mediatek,infracfg: false
214
215 mediatek,sgmiisys:
216 minItems: 1
217 maxItems: 1
218
219 mediatek,wed-pcie: false
220 else:
221 properties:
222 mediatek,pcie-mirror: false
223
224 - if:
225 properties:
226 compatible:
227 contains:
228 const: mediatek,mt7629-eth
229 then:
230 properties:
231 interrupts:
232 minItems: 3
233 maxItems: 3
234
235 clocks:
236 minItems: 17
237 maxItems: 17
238
239 clock-names:
240 items:
241 - const: ethif
242 - const: sgmiitop
243 - const: esw
244 - const: gp0
245 - const: gp1
246 - const: gp2
247 - const: fe
248 - const: sgmii_tx250m
249 - const: sgmii_rx250m
250 - const: sgmii_cdr_ref
251 - const: sgmii_cdr_fb
252 - const: sgmii2_tx250m
253 - const: sgmii2_rx250m
254 - const: sgmii2_cdr_ref
255 - const: sgmii2_cdr_fb
256 - const: sgmii_ck
257 - const: eth2pll
258
259 mediatek,sgmiisys:
260 minItems: 2
261 maxItems: 2
262
263 mediatek,wed: false
264
265 mediatek,wed-pcie: false
266
267 - if:
268 properties:
269 compatible:
270 contains:
271 const: mediatek,mt7981-eth
272 then:
273 properties:
274 interrupts:
275 minItems: 4
276
277 clocks:
278 minItems: 15
279 maxItems: 15
280
281 clock-names:
282 items:
283 - const: fe
284 - const: gp2
285 - const: gp1
286 - const: wocpu0
287 - const: sgmii_ck
288 - const: sgmii_tx250m
289 - const: sgmii_rx250m
290 - const: sgmii_cdr_ref
291 - const: sgmii_cdr_fb
292 - const: sgmii2_tx250m
293 - const: sgmii2_rx250m
294 - const: sgmii2_cdr_ref
295 - const: sgmii2_cdr_fb
296 - const: netsys0
297 - const: netsys1
298
299 mediatek,infracfg: false
300
301 mediatek,sgmiisys:
302 minItems: 2
303 maxItems: 2
304
305 - if:
306 properties:
307 compatible:
308 contains:
309 const: mediatek,mt7986-eth
310 then:
311 properties:
312 interrupts:
313 minItems: 4
314
315 clocks:
316 minItems: 15
317 maxItems: 15
318
319 clock-names:
320 items:
321 - const: fe
322 - const: gp2
323 - const: gp1
324 - const: wocpu1
325 - const: wocpu0
326 - const: sgmii_tx250m
327 - const: sgmii_rx250m
328 - const: sgmii_cdr_ref
329 - const: sgmii_cdr_fb
330 - const: sgmii2_tx250m
331 - const: sgmii2_rx250m
332 - const: sgmii2_cdr_ref
333 - const: sgmii2_cdr_fb
334 - const: netsys0
335 - const: netsys1
336
337 mediatek,infracfg: false
338
339 mediatek,sgmiisys:
340 minItems: 2
341 maxItems: 2
342
343 - if:
344 properties:
345 compatible:
346 contains:
347 const: mediatek,mt7988-eth
348 then:
349 properties:
350 interrupts:
351 minItems: 4
352
353 clocks:
354 minItems: 24
355 maxItems: 24
356
357 clock-names:
358 items:
359 - const: crypto
360 - const: fe
361 - const: gp2
362 - const: gp1
363 - const: gp3
364 - const: ethwarp_wocpu2
365 - const: ethwarp_wocpu1
366 - const: ethwarp_wocpu0
367 - const: esw
368 - const: top_eth_gmii_sel
369 - const: top_eth_refck_50m_sel
370 - const: top_eth_sys_200m_sel
371 - const: top_eth_sys_sel
372 - const: top_eth_xgmii_sel
373 - const: top_eth_mii_sel
374 - const: top_netsys_sel
375 - const: top_netsys_500m_sel
376 - const: top_netsys_pao_2x_sel
377 - const: top_netsys_sync_250m_sel
378 - const: top_netsys_ppefb_250m_sel
379 - const: top_netsys_warp_sel
380 - const: xgp1
381 - const: xgp2
382 - const: xgp3
383
384patternProperties:
385 "^mac@[0-1]$":
386 type: object
387 unevaluatedProperties: false
388 allOf:
389 - $ref: ethernet-controller.yaml#
390 description:
391 Ethernet MAC node
392 properties:
393 compatible:
394 const: mediatek,eth-mac
395
396 reg:
397 maxItems: 1
398
399 required:
400 - reg
401 - compatible
402
403required:
404 - compatible
405 - reg
406 - interrupts
407 - clocks
408 - clock-names
409 - mediatek,ethsys
410
411unevaluatedProperties: false
412
413examples:
414 - |
415 #include <dt-bindings/interrupt-controller/arm-gic.h>
416 #include <dt-bindings/interrupt-controller/irq.h>
417 #include <dt-bindings/clock/mt7622-clk.h>
418 #include <dt-bindings/power/mt7622-power.h>
419
420 soc {
421 #address-cells = <2>;
422 #size-cells = <2>;
423
424 ethernet: ethernet@1b100000 {
425 compatible = "mediatek,mt7622-eth";
426 reg = <0 0x1b100000 0 0x20000>;
427 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
428 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
429 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
430 clocks = <&topckgen CLK_TOP_ETH_SEL>,
431 <ðsys CLK_ETH_ESW_EN>,
432 <ðsys CLK_ETH_GP0_EN>,
433 <ðsys CLK_ETH_GP1_EN>,
434 <ðsys CLK_ETH_GP2_EN>,
435 <&sgmiisys CLK_SGMII_TX250M_EN>,
436 <&sgmiisys CLK_SGMII_RX250M_EN>,
437 <&sgmiisys CLK_SGMII_CDR_REF>,
438 <&sgmiisys CLK_SGMII_CDR_FB>,
439 <&topckgen CLK_TOP_SGMIIPLL>,
440 <&apmixedsys CLK_APMIXED_ETH2PLL>;
441 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
442 "sgmii_tx250m", "sgmii_rx250m",
443 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
444 "eth2pll";
445 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
446 mediatek,ethsys = <ðsys>;
447 mediatek,sgmiisys = <&sgmiisys>;
448 cci-control-port = <&cci_control2>;
449 mediatek,pcie-mirror = <&pcie_mirror>;
450 mediatek,hifsys = <&hifsys>;
451 dma-coherent;
452
453 #address-cells = <1>;
454 #size-cells = <0>;
455
456 mdio0: mdio-bus {
457 #address-cells = <1>;
458 #size-cells = <0>;
459
460 phy0: ethernet-phy@0 {
461 reg = <0>;
462 };
463
464 phy1: ethernet-phy@1 {
465 reg = <1>;
466 };
467 };
468
469 gmac0: mac@0 {
470 compatible = "mediatek,eth-mac";
471 phy-mode = "rgmii";
472 phy-handle = <&phy0>;
473 reg = <0>;
474 };
475
476 gmac1: mac@1 {
477 compatible = "mediatek,eth-mac";
478 phy-mode = "rgmii";
479 phy-handle = <&phy1>;
480 reg = <1>;
481 };
482 };
483 };
484
485 - |
486 #include <dt-bindings/interrupt-controller/arm-gic.h>
487 #include <dt-bindings/interrupt-controller/irq.h>
488 #include <dt-bindings/clock/mt7622-clk.h>
489
490 soc {
491 #address-cells = <2>;
492 #size-cells = <2>;
493
494 eth: ethernet@15100000 {
495 #define CLK_ETH_FE_EN 0
496 #define CLK_ETH_WOCPU1_EN 3
497 #define CLK_ETH_WOCPU0_EN 4
498 #define CLK_TOP_NETSYS_SEL 43
499 #define CLK_TOP_NETSYS_500M_SEL 44
500 #define CLK_TOP_NETSYS_2X_SEL 46
501 #define CLK_TOP_SGM_325M_SEL 47
502 #define CLK_APMIXED_NET2PLL 1
503 #define CLK_APMIXED_SGMPLL 3
504
505 compatible = "mediatek,mt7986-eth";
506 reg = <0 0x15100000 0 0x80000>;
507 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <ðsys CLK_ETH_FE_EN>,
512 <ðsys CLK_ETH_GP2_EN>,
513 <ðsys CLK_ETH_GP1_EN>,
514 <ðsys CLK_ETH_WOCPU1_EN>,
515 <ðsys CLK_ETH_WOCPU0_EN>,
516 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
517 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
518 <&sgmiisys0 CLK_SGMII_CDR_REF>,
519 <&sgmiisys0 CLK_SGMII_CDR_FB>,
520 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
521 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
522 <&sgmiisys1 CLK_SGMII_CDR_REF>,
523 <&sgmiisys1 CLK_SGMII_CDR_FB>,
524 <&topckgen CLK_TOP_NETSYS_SEL>,
525 <&topckgen CLK_TOP_NETSYS_SEL>;
526 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
527 "sgmii_tx250m", "sgmii_rx250m",
528 "sgmii_cdr_ref", "sgmii_cdr_fb",
529 "sgmii2_tx250m", "sgmii2_rx250m",
530 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
531 "netsys0", "netsys1";
532 mediatek,ethsys = <ðsys>;
533 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
534 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
535 <&topckgen CLK_TOP_SGM_325M_SEL>;
536 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
537 <&apmixedsys CLK_APMIXED_SGMPLL>;
538
539 #address-cells = <1>;
540 #size-cells = <0>;
541
542 mdio: mdio-bus {
543 #address-cells = <1>;
544 #size-cells = <0>;
545
546 phy5: ethernet-phy@0 {
547 compatible = "ethernet-phy-id67c9.de0a";
548 phy-mode = "2500base-x";
549 reset-gpios = <&pio 6 1>;
550 reset-deassert-us = <20000>;
551 reg = <5>;
552 };
553
554 phy6: ethernet-phy@1 {
555 compatible = "ethernet-phy-id67c9.de0a";
556 phy-mode = "2500base-x";
557 reg = <6>;
558 };
559 };
560
561 mac0: mac@0 {
562 compatible = "mediatek,eth-mac";
563 phy-mode = "2500base-x";
564 phy-handle = <&phy5>;
565 reg = <0>;
566 };
567
568 mac1: mac@1 {
569 compatible = "mediatek,eth-mac";
570 phy-mode = "2500base-x";
571 phy-handle = <&phy6>;
572 reg = <1>;
573 };
574 };
575 };