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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8450 Display MDSS
8
9maintainers:
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19 compatible:
20 const: qcom,sm8450-mdss
21
22 clocks:
23 items:
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display sf AXI
27 - description: Display core
28
29 iommus:
30 maxItems: 1
31
32 interconnects:
33 maxItems: 3
34
35 interconnect-names:
36 maxItems: 3
37
38patternProperties:
39 "^display-controller@[0-9a-f]+$":
40 type: object
41 additionalProperties: true
42
43 properties:
44 compatible:
45 const: qcom,sm8450-dpu
46
47 "^displayport-controller@[0-9a-f]+$":
48 type: object
49 additionalProperties: true
50
51 properties:
52 compatible:
53 items:
54 - const: qcom,sm8450-dp
55 - const: qcom,sm8350-dp
56
57 "^dsi@[0-9a-f]+$":
58 type: object
59 additionalProperties: true
60
61 properties:
62 compatible:
63 items:
64 - const: qcom,sm8450-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
66
67 "^phy@[0-9a-f]+$":
68 type: object
69 additionalProperties: true
70
71 properties:
72 compatible:
73 const: qcom,sm8450-dsi-phy-5nm
74
75required:
76 - compatible
77
78unevaluatedProperties: false
79
80examples:
81 - |
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
83 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,sm8450.h>
87 #include <dt-bindings/power/qcom,rpmhpd.h>
88
89 display-subsystem@ae00000 {
90 compatible = "qcom,sm8450-mdss";
91 reg = <0x0ae00000 0x1000>;
92 reg-names = "mdss";
93
94 interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
95 <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
96 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
97 interconnect-names = "mdp0-mem",
98 "mdp1-mem",
99 "cpu-cfg";
100
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
102
103 power-domains = <&dispcc MDSS_GDSC>;
104
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&gcc GCC_DISP_HF_AXI_CLK>,
107 <&gcc GCC_DISP_SF_AXI_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
109 clock-names = "iface", "bus", "nrt_bus", "core";
110
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
114
115 iommus = <&apps_smmu 0x2800 0x402>;
116
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges;
120
121 display-controller@ae01000 {
122 compatible = "qcom,sm8450-dpu";
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
125 reg-names = "mdp", "vbif";
126
127 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
128 <&gcc GCC_DISP_SF_AXI_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 clock-names = "bus",
134 "nrt_bus",
135 "iface",
136 "lut",
137 "core",
138 "vsync";
139
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141 assigned-clock-rates = <19200000>;
142
143 operating-points-v2 = <&mdp_opp_table>;
144 power-domains = <&rpmhpd RPMHPD_MMCX>;
145
146 interrupt-parent = <&mdss>;
147 interrupts = <0>;
148
149 ports {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 port@0 {
154 reg = <0>;
155 dpu_intf1_out: endpoint {
156 remote-endpoint = <&dsi0_in>;
157 };
158 };
159
160 port@1 {
161 reg = <1>;
162 dpu_intf2_out: endpoint {
163 remote-endpoint = <&dsi1_in>;
164 };
165 };
166 };
167
168 mdp_opp_table: opp-table {
169 compatible = "operating-points-v2";
170
171 opp-172000000{
172 opp-hz = /bits/ 64 <172000000>;
173 required-opps = <&rpmhpd_opp_low_svs_d1>;
174 };
175
176 opp-200000000 {
177 opp-hz = /bits/ 64 <200000000>;
178 required-opps = <&rpmhpd_opp_low_svs>;
179 };
180
181 opp-325000000 {
182 opp-hz = /bits/ 64 <325000000>;
183 required-opps = <&rpmhpd_opp_svs>;
184 };
185
186 opp-375000000 {
187 opp-hz = /bits/ 64 <375000000>;
188 required-opps = <&rpmhpd_opp_svs_l1>;
189 };
190
191 opp-500000000 {
192 opp-hz = /bits/ 64 <500000000>;
193 required-opps = <&rpmhpd_opp_nom>;
194 };
195 };
196 };
197
198 dsi@ae94000 {
199 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
200 reg = <0x0ae94000 0x400>;
201 reg-names = "dsi_ctrl";
202
203 interrupt-parent = <&mdss>;
204 interrupts = <4>;
205
206 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
207 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
208 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
209 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
210 <&dispcc DISP_CC_MDSS_AHB_CLK>,
211 <&gcc GCC_DISP_HF_AXI_CLK>;
212 clock-names = "byte",
213 "byte_intf",
214 "pixel",
215 "core",
216 "iface",
217 "bus";
218
219 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
220 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
221 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
222
223 operating-points-v2 = <&dsi_opp_table>;
224 power-domains = <&rpmhpd RPMHPD_MMCX>;
225
226 phys = <&dsi0_phy>;
227 phy-names = "dsi";
228
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 ports {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 port@0 {
237 reg = <0>;
238 dsi0_in: endpoint {
239 remote-endpoint = <&dpu_intf1_out>;
240 };
241 };
242
243 port@1 {
244 reg = <1>;
245 dsi0_out: endpoint {
246 };
247 };
248 };
249
250 dsi_opp_table: opp-table {
251 compatible = "operating-points-v2";
252
253 opp-160310000{
254 opp-hz = /bits/ 64 <160310000>;
255 required-opps = <&rpmhpd_opp_low_svs_d1>;
256 };
257
258 opp-187500000 {
259 opp-hz = /bits/ 64 <187500000>;
260 required-opps = <&rpmhpd_opp_low_svs>;
261 };
262
263 opp-300000000 {
264 opp-hz = /bits/ 64 <300000000>;
265 required-opps = <&rpmhpd_opp_svs>;
266 };
267
268 opp-358000000 {
269 opp-hz = /bits/ 64 <358000000>;
270 required-opps = <&rpmhpd_opp_svs_l1>;
271 };
272 };
273 };
274
275 dsi0_phy: phy@ae94400 {
276 compatible = "qcom,sm8450-dsi-phy-5nm";
277 reg = <0x0ae94400 0x200>,
278 <0x0ae94600 0x280>,
279 <0x0ae94900 0x260>;
280 reg-names = "dsi_phy",
281 "dsi_phy_lane",
282 "dsi_pll";
283
284 #clock-cells = <1>;
285 #phy-cells = <0>;
286
287 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
288 <&rpmhcc RPMH_CXO_CLK>;
289 clock-names = "iface", "ref";
290 vdds-supply = <&vreg_dsi_phy>;
291 };
292
293 dsi@ae96000 {
294 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
295 reg = <0x0ae96000 0x400>;
296 reg-names = "dsi_ctrl";
297
298 interrupt-parent = <&mdss>;
299 interrupts = <5>;
300
301 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
302 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
303 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
304 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
305 <&dispcc DISP_CC_MDSS_AHB_CLK>,
306 <&gcc GCC_DISP_HF_AXI_CLK>;
307 clock-names = "byte",
308 "byte_intf",
309 "pixel",
310 "core",
311 "iface",
312 "bus";
313
314 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
315 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
316 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
317
318 operating-points-v2 = <&dsi_opp_table>;
319 power-domains = <&rpmhpd RPMHPD_MMCX>;
320
321 phys = <&dsi1_phy>;
322 phy-names = "dsi";
323
324 #address-cells = <1>;
325 #size-cells = <0>;
326
327 ports {
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 port@0 {
332 reg = <0>;
333 dsi1_in: endpoint {
334 remote-endpoint = <&dpu_intf2_out>;
335 };
336 };
337
338 port@1 {
339 reg = <1>;
340 dsi1_out: endpoint {
341 };
342 };
343 };
344 };
345
346 dsi1_phy: phy@ae96400 {
347 compatible = "qcom,sm8450-dsi-phy-5nm";
348 reg = <0x0ae96400 0x200>,
349 <0x0ae96600 0x280>,
350 <0x0ae96900 0x260>;
351 reg-names = "dsi_phy",
352 "dsi_phy_lane",
353 "dsi_pll";
354
355 #clock-cells = <1>;
356 #phy-cells = <0>;
357
358 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
359 <&rpmhcc RPMH_CXO_CLK>;
360 clock-names = "iface", "ref";
361 vdds-supply = <&vreg_dsi_phy>;
362 };
363 };
364...