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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Mobile Display SubSystem (MDSS)
8
9maintainers:
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
12
13description:
14 This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
16
17properties:
18 $nodename:
19 pattern: "^display-subsystem@[0-9a-f]+$"
20
21 compatible:
22 enum:
23 - qcom,mdss
24
25 reg:
26 minItems: 2
27 maxItems: 3
28
29 reg-names:
30 minItems: 2
31 items:
32 - const: mdss_phys
33 - const: vbif_phys
34 - const: vbif_nrt_phys
35
36 interrupts:
37 maxItems: 1
38
39 interrupt-controller: true
40
41 "#interrupt-cells":
42 const: 1
43
44 power-domains:
45 maxItems: 1
46 description: |
47 The MDSS power domain provided by GCC
48
49 clocks:
50 oneOf:
51 - minItems: 3
52 items:
53 - description: Display abh clock
54 - description: Display axi clock
55 - description: Display vsync clock
56 - description: Display core clock
57 - minItems: 1
58 items:
59 - description: Display abh clock
60 - description: Display core clock
61
62 clock-names:
63 oneOf:
64 - minItems: 3
65 items:
66 - const: iface
67 - const: bus
68 - const: vsync
69 - const: core
70 - minItems: 1
71 items:
72 - const: iface
73 - const: core
74
75 "#address-cells":
76 const: 1
77
78 "#size-cells":
79 const: 1
80
81 ranges: true
82
83 resets:
84 items:
85 - description: MDSS_CORE reset
86
87required:
88 - compatible
89 - reg
90 - reg-names
91 - interrupts
92 - interrupt-controller
93 - "#interrupt-cells"
94 - power-domains
95 - clocks
96 - clock-names
97 - "#address-cells"
98 - "#size-cells"
99 - ranges
100
101patternProperties:
102 "^display-controller@[1-9a-f][0-9a-f]*$":
103 type: object
104 additionalProperties: true
105 properties:
106 compatible:
107 contains:
108 const: qcom,mdp5
109
110 "^dsi@[1-9a-f][0-9a-f]*$":
111 type: object
112 additionalProperties: true
113 properties:
114 compatible:
115 contains:
116 const: qcom,mdss-dsi-ctrl
117
118 "^phy@[1-9a-f][0-9a-f]*$":
119 type: object
120 additionalProperties: true
121 properties:
122 compatible:
123 enum:
124 - qcom,dsi-phy-14nm
125 - qcom,dsi-phy-14nm-660
126 - qcom,dsi-phy-14nm-8953
127 - qcom,dsi-phy-20nm
128 - qcom,dsi-phy-28nm-8226
129 - qcom,dsi-phy-28nm-8937
130 - qcom,dsi-phy-28nm-hpm
131 - qcom,dsi-phy-28nm-hpm-fam-b
132 - qcom,dsi-phy-28nm-lp
133 - qcom,hdmi-phy-8084
134 - qcom,hdmi-phy-8660
135 - qcom,hdmi-phy-8960
136 - qcom,hdmi-phy-8974
137 - qcom,hdmi-phy-8996
138
139 "^hdmi-tx@[1-9a-f][0-9a-f]*$":
140 type: object
141 additionalProperties: true
142 properties:
143 compatible:
144 enum:
145 - qcom,hdmi-tx-8084
146 - qcom,hdmi-tx-8660
147 - qcom,hdmi-tx-8960
148 - qcom,hdmi-tx-8974
149 - qcom,hdmi-tx-8994
150 - qcom,hdmi-tx-8996
151
152additionalProperties: false
153
154examples:
155 - |
156 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
157 #include <dt-bindings/interrupt-controller/arm-gic.h>
158 display-subsystem@1a00000 {
159 compatible = "qcom,mdss";
160 reg = <0x1a00000 0x1000>,
161 <0x1ac8000 0x3000>;
162 reg-names = "mdss_phys", "vbif_phys";
163
164 power-domains = <&gcc MDSS_GDSC>;
165
166 clocks = <&gcc GCC_MDSS_AHB_CLK>,
167 <&gcc GCC_MDSS_AXI_CLK>,
168 <&gcc GCC_MDSS_VSYNC_CLK>;
169 clock-names = "iface",
170 "bus",
171 "vsync";
172
173 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
174
175 interrupt-controller;
176 #interrupt-cells = <1>;
177
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges;
181
182 display-controller@1a01000 {
183 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
184 reg = <0x01a01000 0x89000>;
185 reg-names = "mdp_phys";
186
187 interrupt-parent = <&mdss>;
188 interrupts = <0>;
189
190 clocks = <&gcc GCC_MDSS_AHB_CLK>,
191 <&gcc GCC_MDSS_AXI_CLK>,
192 <&gcc GCC_MDSS_MDP_CLK>,
193 <&gcc GCC_MDSS_VSYNC_CLK>;
194 clock-names = "iface",
195 "bus",
196 "core",
197 "vsync";
198
199 iommus = <&apps_iommu 4>;
200
201 ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
204
205 port@0 {
206 reg = <0>;
207 mdp5_intf1_out: endpoint {
208 remote-endpoint = <&dsi0_in>;
209 };
210 };
211 };
212 };
213 };
214...