tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 */
7
8#include <linux/device.h>
9#include <linux/interconnect.h>
10#include <linux/interconnect-provider.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <dt-bindings/interconnect/qcom,sc7280.h>
15
16#include "bcm-voter.h"
17#include "icc-rpmh.h"
18#include "sc7280.h"
19
20static struct qcom_icc_node qhm_qspi = {
21 .name = "qhm_qspi",
22 .id = SC7280_MASTER_QSPI_0,
23 .channels = 1,
24 .buswidth = 4,
25 .qosbox = &(const struct qcom_icc_qosbox) {
26 .num_ports = 1,
27 .port_offsets = { 0x7000 },
28 .prio = 2,
29 .urg_fwd = 0,
30 },
31 .num_links = 1,
32 .links = { SC7280_SLAVE_A1NOC_SNOC },
33};
34
35static struct qcom_icc_node qhm_qup0 = {
36 .name = "qhm_qup0",
37 .id = SC7280_MASTER_QUP_0,
38 .channels = 1,
39 .buswidth = 4,
40 .qosbox = &(const struct qcom_icc_qosbox) {
41 .num_ports = 1,
42 .port_offsets = { 0x11000 },
43 .prio = 2,
44 .urg_fwd = 0,
45 },
46 .num_links = 1,
47 .links = { SC7280_SLAVE_A1NOC_SNOC },
48};
49
50static struct qcom_icc_node qhm_qup1 = {
51 .name = "qhm_qup1",
52 .id = SC7280_MASTER_QUP_1,
53 .channels = 1,
54 .buswidth = 4,
55 .qosbox = &(const struct qcom_icc_qosbox) {
56 .num_ports = 1,
57 .port_offsets = { 0x8000 },
58 .prio = 2,
59 .urg_fwd = 0,
60 },
61 .num_links = 1,
62 .links = { SC7280_SLAVE_A1NOC_SNOC },
63};
64
65static struct qcom_icc_node qnm_a1noc_cfg = {
66 .name = "qnm_a1noc_cfg",
67 .id = SC7280_MASTER_A1NOC_CFG,
68 .channels = 1,
69 .buswidth = 4,
70 .num_links = 1,
71 .links = { SC7280_SLAVE_SERVICE_A1NOC },
72};
73
74static struct qcom_icc_node xm_sdc1 = {
75 .name = "xm_sdc1",
76 .id = SC7280_MASTER_SDCC_1,
77 .channels = 1,
78 .buswidth = 8,
79 .qosbox = &(const struct qcom_icc_qosbox) {
80 .num_ports = 1,
81 .port_offsets = { 0xc000 },
82 .prio = 2,
83 .urg_fwd = 0,
84 },
85 .num_links = 1,
86 .links = { SC7280_SLAVE_A1NOC_SNOC },
87};
88
89static struct qcom_icc_node xm_sdc2 = {
90 .name = "xm_sdc2",
91 .id = SC7280_MASTER_SDCC_2,
92 .channels = 1,
93 .buswidth = 8,
94 .qosbox = &(const struct qcom_icc_qosbox) {
95 .num_ports = 1,
96 .port_offsets = { 0xe000 },
97 .prio = 2,
98 .urg_fwd = 0,
99 },
100 .num_links = 1,
101 .links = { SC7280_SLAVE_A1NOC_SNOC },
102};
103
104static struct qcom_icc_node xm_sdc4 = {
105 .name = "xm_sdc4",
106 .id = SC7280_MASTER_SDCC_4,
107 .channels = 1,
108 .buswidth = 8,
109 .qosbox = &(const struct qcom_icc_qosbox) {
110 .num_ports = 1,
111 .port_offsets = { 0x9000 },
112 .prio = 2,
113 .urg_fwd = 0,
114 },
115 .num_links = 1,
116 .links = { SC7280_SLAVE_A1NOC_SNOC },
117};
118
119static struct qcom_icc_node xm_ufs_mem = {
120 .name = "xm_ufs_mem",
121 .id = SC7280_MASTER_UFS_MEM,
122 .channels = 1,
123 .buswidth = 8,
124 .qosbox = &(const struct qcom_icc_qosbox) {
125 .num_ports = 1,
126 .port_offsets = { 0xa000 },
127 .prio = 2,
128 .urg_fwd = 0,
129 },
130 .num_links = 1,
131 .links = { SC7280_SLAVE_A1NOC_SNOC },
132};
133
134static struct qcom_icc_node xm_usb2 = {
135 .name = "xm_usb2",
136 .id = SC7280_MASTER_USB2,
137 .channels = 1,
138 .buswidth = 8,
139 .num_links = 1,
140 .links = { SC7280_SLAVE_A1NOC_SNOC },
141};
142
143static struct qcom_icc_node xm_usb3_0 = {
144 .name = "xm_usb3_0",
145 .id = SC7280_MASTER_USB3_0,
146 .channels = 1,
147 .buswidth = 8,
148 .qosbox = &(const struct qcom_icc_qosbox) {
149 .num_ports = 1,
150 .port_offsets = { 0xb000 },
151 .prio = 2,
152 .urg_fwd = 0,
153 },
154 .num_links = 1,
155 .links = { SC7280_SLAVE_A1NOC_SNOC },
156};
157
158static struct qcom_icc_node qhm_qdss_bam = {
159 .name = "qhm_qdss_bam",
160 .id = SC7280_MASTER_QDSS_BAM,
161 .channels = 1,
162 .buswidth = 4,
163 .qosbox = &(const struct qcom_icc_qosbox) {
164 .num_ports = 1,
165 .port_offsets = { 0x18000 },
166 .prio = 2,
167 .urg_fwd = 0,
168 },
169 .num_links = 1,
170 .links = { SC7280_SLAVE_A2NOC_SNOC },
171};
172
173static struct qcom_icc_node qnm_a2noc_cfg = {
174 .name = "qnm_a2noc_cfg",
175 .id = SC7280_MASTER_A2NOC_CFG,
176 .channels = 1,
177 .buswidth = 4,
178 .num_links = 1,
179 .links = { SC7280_SLAVE_SERVICE_A2NOC },
180};
181
182static struct qcom_icc_node qnm_cnoc_datapath = {
183 .name = "qnm_cnoc_datapath",
184 .id = SC7280_MASTER_CNOC_A2NOC,
185 .channels = 1,
186 .buswidth = 8,
187 .qosbox = &(const struct qcom_icc_qosbox) {
188 .num_ports = 1,
189 .port_offsets = { 0x1c000 },
190 .prio = 2,
191 .urg_fwd = 0,
192 },
193 .num_links = 1,
194 .links = { SC7280_SLAVE_A2NOC_SNOC },
195};
196
197static struct qcom_icc_node qxm_crypto = {
198 .name = "qxm_crypto",
199 .id = SC7280_MASTER_CRYPTO,
200 .channels = 1,
201 .buswidth = 8,
202 .qosbox = &(const struct qcom_icc_qosbox) {
203 .num_ports = 1,
204 .port_offsets = { 0x1d000 },
205 .prio = 2,
206 .urg_fwd = 0,
207 },
208 .num_links = 1,
209 .links = { SC7280_SLAVE_A2NOC_SNOC },
210};
211
212static struct qcom_icc_node qxm_ipa = {
213 .name = "qxm_ipa",
214 .id = SC7280_MASTER_IPA,
215 .channels = 1,
216 .buswidth = 8,
217 .qosbox = &(const struct qcom_icc_qosbox) {
218 .num_ports = 1,
219 .port_offsets = { 0x10000 },
220 .prio = 2,
221 .urg_fwd = 0,
222 },
223 .num_links = 1,
224 .links = { SC7280_SLAVE_A2NOC_SNOC },
225};
226
227static struct qcom_icc_node xm_pcie3_0 = {
228 .name = "xm_pcie3_0",
229 .id = SC7280_MASTER_PCIE_0,
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
234};
235
236static struct qcom_icc_node xm_pcie3_1 = {
237 .name = "xm_pcie3_1",
238 .id = SC7280_MASTER_PCIE_1,
239 .channels = 1,
240 .buswidth = 8,
241 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
242};
243
244static struct qcom_icc_node xm_qdss_etr = {
245 .name = "xm_qdss_etr",
246 .id = SC7280_MASTER_QDSS_ETR,
247 .channels = 1,
248 .buswidth = 8,
249 .qosbox = &(const struct qcom_icc_qosbox) {
250 .num_ports = 1,
251 .port_offsets = { 0x15000 },
252 .prio = 2,
253 .urg_fwd = 0,
254 },
255 .num_links = 1,
256 .links = { SC7280_SLAVE_A2NOC_SNOC },
257};
258
259static struct qcom_icc_node qup0_core_master = {
260 .name = "qup0_core_master",
261 .id = SC7280_MASTER_QUP_CORE_0,
262 .channels = 1,
263 .buswidth = 4,
264 .num_links = 1,
265 .links = { SC7280_SLAVE_QUP_CORE_0 },
266};
267
268static struct qcom_icc_node qup1_core_master = {
269 .name = "qup1_core_master",
270 .id = SC7280_MASTER_QUP_CORE_1,
271 .channels = 1,
272 .buswidth = 4,
273 .num_links = 1,
274 .links = { SC7280_SLAVE_QUP_CORE_1 },
275};
276
277static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
278 .name = "qnm_cnoc3_cnoc2",
279 .id = SC7280_MASTER_CNOC3_CNOC2,
280 .channels = 1,
281 .buswidth = 8,
282 .num_links = 44,
283 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
284 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
285 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
286 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
287 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
288 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
289 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
290 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
291 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
292 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
293 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
294 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
295 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
296 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
297 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
298 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
299 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
300 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
301 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
302 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
303 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
304 SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
305};
306
307static struct qcom_icc_node xm_qdss_dap = {
308 .name = "xm_qdss_dap",
309 .id = SC7280_MASTER_QDSS_DAP,
310 .channels = 1,
311 .buswidth = 8,
312 .num_links = 45,
313 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
314 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
315 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
316 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
317 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
318 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
319 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
320 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
321 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
322 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
323 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
324 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
325 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
326 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
327 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
328 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
329 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
330 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
331 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
332 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
333 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
334 SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
335 SC7280_SLAVE_SNOC_CFG },
336};
337
338static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
339 .name = "qnm_cnoc2_cnoc3",
340 .id = SC7280_MASTER_CNOC2_CNOC3,
341 .channels = 1,
342 .buswidth = 8,
343 .num_links = 9,
344 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
345 SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
346 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
347 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
348 SC7280_SLAVE_TCU },
349};
350
351static struct qcom_icc_node qnm_gemnoc_cnoc = {
352 .name = "qnm_gemnoc_cnoc",
353 .id = SC7280_MASTER_GEM_NOC_CNOC,
354 .channels = 1,
355 .buswidth = 16,
356 .num_links = 9,
357 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
358 SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
359 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
360 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
361 SC7280_SLAVE_TCU },
362};
363
364static struct qcom_icc_node qnm_gemnoc_pcie = {
365 .name = "qnm_gemnoc_pcie",
366 .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
367 .channels = 1,
368 .buswidth = 8,
369 .num_links = 2,
370 .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
371};
372
373static struct qcom_icc_node qnm_cnoc_dc_noc = {
374 .name = "qnm_cnoc_dc_noc",
375 .id = SC7280_MASTER_CNOC_DC_NOC,
376 .channels = 1,
377 .buswidth = 4,
378 .num_links = 2,
379 .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
380};
381
382static struct qcom_icc_node alm_gpu_tcu = {
383 .name = "alm_gpu_tcu",
384 .id = SC7280_MASTER_GPU_TCU,
385 .channels = 1,
386 .buswidth = 8,
387 .qosbox = &(const struct qcom_icc_qosbox) {
388 .num_ports = 1,
389 .port_offsets = { 0xd7000 },
390 .prio = 2,
391 .urg_fwd = 0,
392 },
393 .num_links = 2,
394 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
395};
396
397static struct qcom_icc_node alm_sys_tcu = {
398 .name = "alm_sys_tcu",
399 .id = SC7280_MASTER_SYS_TCU,
400 .channels = 1,
401 .buswidth = 8,
402 .qosbox = &(const struct qcom_icc_qosbox) {
403 .num_ports = 1,
404 .port_offsets = { 0xd6000 },
405 .prio = 6,
406 .urg_fwd = 0,
407 },
408 .num_links = 2,
409 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
410};
411
412static struct qcom_icc_node chm_apps = {
413 .name = "chm_apps",
414 .id = SC7280_MASTER_APPSS_PROC,
415 .channels = 1,
416 .buswidth = 32,
417 .num_links = 3,
418 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
419 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
420};
421
422static struct qcom_icc_node qnm_cmpnoc = {
423 .name = "qnm_cmpnoc",
424 .id = SC7280_MASTER_COMPUTE_NOC,
425 .channels = 2,
426 .buswidth = 32,
427 .qosbox = &(const struct qcom_icc_qosbox) {
428 .num_ports = 2,
429 .port_offsets = { 0x21000, 0x61000 },
430 .prio = 0,
431 .urg_fwd = 1,
432 },
433 .num_links = 2,
434 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
435};
436
437static struct qcom_icc_node qnm_gemnoc_cfg = {
438 .name = "qnm_gemnoc_cfg",
439 .id = SC7280_MASTER_GEM_NOC_CFG,
440 .channels = 1,
441 .buswidth = 4,
442 .num_links = 5,
443 .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
444 SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
445 SC7280_SLAVE_SERVICE_GEM_NOC },
446};
447
448static struct qcom_icc_node qnm_gpu = {
449 .name = "qnm_gpu",
450 .id = SC7280_MASTER_GFX3D,
451 .channels = 2,
452 .buswidth = 32,
453 .qosbox = &(const struct qcom_icc_qosbox) {
454 .num_ports = 2,
455 .port_offsets = { 0x22000, 0x62000 },
456 .prio = 0,
457 .urg_fwd = 0,
458 },
459 .num_links = 2,
460 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
461};
462
463static struct qcom_icc_node qnm_mnoc_hf = {
464 .name = "qnm_mnoc_hf",
465 .id = SC7280_MASTER_MNOC_HF_MEM_NOC,
466 .channels = 2,
467 .buswidth = 32,
468 .qosbox = &(const struct qcom_icc_qosbox) {
469 .num_ports = 2,
470 .port_offsets = { 0x23000, 0x63000 },
471 .prio = 0,
472 .urg_fwd = 1,
473 },
474 .num_links = 1,
475 .links = { SC7280_SLAVE_LLCC },
476};
477
478static struct qcom_icc_node qnm_mnoc_sf = {
479 .name = "qnm_mnoc_sf",
480 .id = SC7280_MASTER_MNOC_SF_MEM_NOC,
481 .channels = 1,
482 .buswidth = 32,
483 .qosbox = &(const struct qcom_icc_qosbox) {
484 .num_ports = 1,
485 .port_offsets = { 0xcf000 },
486 .prio = 0,
487 .urg_fwd = 1,
488 },
489 .num_links = 2,
490 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
491};
492
493static struct qcom_icc_node qnm_pcie = {
494 .name = "qnm_pcie",
495 .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
496 .channels = 1,
497 .buswidth = 16,
498 .num_links = 2,
499 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
500};
501
502static struct qcom_icc_node qnm_snoc_gc = {
503 .name = "qnm_snoc_gc",
504 .id = SC7280_MASTER_SNOC_GC_MEM_NOC,
505 .channels = 1,
506 .buswidth = 8,
507 .qosbox = &(const struct qcom_icc_qosbox) {
508 .num_ports = 1,
509 .port_offsets = { 0xd3000 },
510 .prio = 0,
511 .urg_fwd = 1,
512 },
513 .num_links = 1,
514 .links = { SC7280_SLAVE_LLCC },
515};
516
517static struct qcom_icc_node qnm_snoc_sf = {
518 .name = "qnm_snoc_sf",
519 .id = SC7280_MASTER_SNOC_SF_MEM_NOC,
520 .channels = 1,
521 .buswidth = 16,
522 .qosbox = &(const struct qcom_icc_qosbox) {
523 .num_ports = 1,
524 .port_offsets = { 0xd4000 },
525 .prio = 0,
526 .urg_fwd = 1,
527 },
528 .num_links = 3,
529 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
530 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
531};
532
533static struct qcom_icc_node qhm_config_noc = {
534 .name = "qhm_config_noc",
535 .id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
536 .channels = 1,
537 .buswidth = 4,
538 .num_links = 6,
539 .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
540 SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
541 SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
542};
543
544static struct qcom_icc_node llcc_mc = {
545 .name = "llcc_mc",
546 .id = SC7280_MASTER_LLCC,
547 .channels = 2,
548 .buswidth = 4,
549 .num_links = 1,
550 .links = { SC7280_SLAVE_EBI1 },
551};
552
553static struct qcom_icc_node qnm_mnoc_cfg = {
554 .name = "qnm_mnoc_cfg",
555 .id = SC7280_MASTER_CNOC_MNOC_CFG,
556 .channels = 1,
557 .buswidth = 4,
558 .num_links = 1,
559 .links = { SC7280_SLAVE_SERVICE_MNOC },
560};
561
562static struct qcom_icc_node qnm_video0 = {
563 .name = "qnm_video0",
564 .id = SC7280_MASTER_VIDEO_P0,
565 .channels = 1,
566 .buswidth = 32,
567 .qosbox = &(const struct qcom_icc_qosbox) {
568 .num_ports = 1,
569 .port_offsets = { 0x14000 },
570 .prio = 0,
571 .urg_fwd = 1,
572 },
573 .num_links = 1,
574 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
575};
576
577static struct qcom_icc_node qnm_video_cpu = {
578 .name = "qnm_video_cpu",
579 .id = SC7280_MASTER_VIDEO_PROC,
580 .channels = 1,
581 .buswidth = 8,
582 .qosbox = &(const struct qcom_icc_qosbox) {
583 .num_ports = 1,
584 .port_offsets = { 0x15000 },
585 .prio = 0,
586 .urg_fwd = 1,
587 },
588 .num_links = 1,
589 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
590};
591
592static struct qcom_icc_node qxm_camnoc_hf = {
593 .name = "qxm_camnoc_hf",
594 .id = SC7280_MASTER_CAMNOC_HF,
595 .channels = 2,
596 .buswidth = 32,
597 .qosbox = &(const struct qcom_icc_qosbox) {
598 .num_ports = 2,
599 .port_offsets = { 0x10000, 0x10180 },
600 .prio = 0,
601 .urg_fwd = 1,
602 },
603 .num_links = 1,
604 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
605};
606
607static struct qcom_icc_node qxm_camnoc_icp = {
608 .name = "qxm_camnoc_icp",
609 .id = SC7280_MASTER_CAMNOC_ICP,
610 .channels = 1,
611 .buswidth = 8,
612 .qosbox = &(const struct qcom_icc_qosbox) {
613 .num_ports = 1,
614 .port_offsets = { 0x11000 },
615 .prio = 0,
616 .urg_fwd = 1,
617 },
618 .num_links = 1,
619 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
620};
621
622static struct qcom_icc_node qxm_camnoc_sf = {
623 .name = "qxm_camnoc_sf",
624 .id = SC7280_MASTER_CAMNOC_SF,
625 .channels = 1,
626 .buswidth = 32,
627 .qosbox = &(const struct qcom_icc_qosbox) {
628 .num_ports = 1,
629 .port_offsets = { 0x12000 },
630 .prio = 0,
631 .urg_fwd = 1,
632 },
633 .num_links = 1,
634 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
635};
636
637static struct qcom_icc_node qxm_mdp0 = {
638 .name = "qxm_mdp0",
639 .id = SC7280_MASTER_MDP0,
640 .channels = 1,
641 .buswidth = 32,
642 .qosbox = &(const struct qcom_icc_qosbox) {
643 .num_ports = 1,
644 .port_offsets = { 0x16000 },
645 .prio = 0,
646 .urg_fwd = 1,
647 },
648 .num_links = 1,
649 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
650};
651
652static struct qcom_icc_node qhm_nsp_noc_config = {
653 .name = "qhm_nsp_noc_config",
654 .id = SC7280_MASTER_CDSP_NOC_CFG,
655 .channels = 1,
656 .buswidth = 4,
657 .num_links = 1,
658 .links = { SC7280_SLAVE_SERVICE_NSP_NOC },
659};
660
661static struct qcom_icc_node qxm_nsp = {
662 .name = "qxm_nsp",
663 .id = SC7280_MASTER_CDSP_PROC,
664 .channels = 2,
665 .buswidth = 32,
666 .num_links = 1,
667 .links = { SC7280_SLAVE_CDSP_MEM_NOC },
668};
669
670static struct qcom_icc_node qnm_aggre1_noc = {
671 .name = "qnm_aggre1_noc",
672 .id = SC7280_MASTER_A1NOC_SNOC,
673 .channels = 1,
674 .buswidth = 16,
675 .num_links = 1,
676 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
677};
678
679static struct qcom_icc_node qnm_aggre2_noc = {
680 .name = "qnm_aggre2_noc",
681 .id = SC7280_MASTER_A2NOC_SNOC,
682 .channels = 1,
683 .buswidth = 16,
684 .num_links = 1,
685 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
686};
687
688static struct qcom_icc_node qnm_snoc_cfg = {
689 .name = "qnm_snoc_cfg",
690 .id = SC7280_MASTER_SNOC_CFG,
691 .channels = 1,
692 .buswidth = 4,
693 .num_links = 1,
694 .links = { SC7280_SLAVE_SERVICE_SNOC },
695};
696
697static struct qcom_icc_node qxm_pimem = {
698 .name = "qxm_pimem",
699 .id = SC7280_MASTER_PIMEM,
700 .channels = 1,
701 .buswidth = 8,
702 .qosbox = &(const struct qcom_icc_qosbox) {
703 .num_ports = 1,
704 .port_offsets = { 0x8000 },
705 .prio = 2,
706 .urg_fwd = 0,
707 },
708 .num_links = 1,
709 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
710};
711
712static struct qcom_icc_node xm_gic = {
713 .name = "xm_gic",
714 .id = SC7280_MASTER_GIC,
715 .channels = 1,
716 .buswidth = 8,
717 .qosbox = &(const struct qcom_icc_qosbox) {
718 .num_ports = 1,
719 .port_offsets = { 0xa000 },
720 .prio = 2,
721 .urg_fwd = 0,
722 },
723 .num_links = 1,
724 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
725};
726
727static struct qcom_icc_node qns_a1noc_snoc = {
728 .name = "qns_a1noc_snoc",
729 .id = SC7280_SLAVE_A1NOC_SNOC,
730 .channels = 1,
731 .buswidth = 16,
732 .num_links = 1,
733 .links = { SC7280_MASTER_A1NOC_SNOC },
734};
735
736static struct qcom_icc_node srvc_aggre1_noc = {
737 .name = "srvc_aggre1_noc",
738 .id = SC7280_SLAVE_SERVICE_A1NOC,
739 .channels = 1,
740 .buswidth = 4,
741 .num_links = 0,
742};
743
744static struct qcom_icc_node qns_a2noc_snoc = {
745 .name = "qns_a2noc_snoc",
746 .id = SC7280_SLAVE_A2NOC_SNOC,
747 .channels = 1,
748 .buswidth = 16,
749 .num_links = 1,
750 .links = { SC7280_MASTER_A2NOC_SNOC },
751};
752
753static struct qcom_icc_node qns_pcie_mem_noc = {
754 .name = "qns_pcie_mem_noc",
755 .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
756 .channels = 1,
757 .buswidth = 16,
758 .num_links = 1,
759 .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
760};
761
762static struct qcom_icc_node srvc_aggre2_noc = {
763 .name = "srvc_aggre2_noc",
764 .id = SC7280_SLAVE_SERVICE_A2NOC,
765 .channels = 1,
766 .buswidth = 4,
767 .num_links = 0,
768};
769
770static struct qcom_icc_node qup0_core_slave = {
771 .name = "qup0_core_slave",
772 .id = SC7280_SLAVE_QUP_CORE_0,
773 .channels = 1,
774 .buswidth = 4,
775 .num_links = 0,
776};
777
778static struct qcom_icc_node qup1_core_slave = {
779 .name = "qup1_core_slave",
780 .id = SC7280_SLAVE_QUP_CORE_1,
781 .channels = 1,
782 .buswidth = 4,
783 .num_links = 0,
784};
785
786static struct qcom_icc_node qhs_ahb2phy0 = {
787 .name = "qhs_ahb2phy0",
788 .id = SC7280_SLAVE_AHB2PHY_SOUTH,
789 .channels = 1,
790 .buswidth = 4,
791 .num_links = 0,
792};
793
794static struct qcom_icc_node qhs_ahb2phy1 = {
795 .name = "qhs_ahb2phy1",
796 .id = SC7280_SLAVE_AHB2PHY_NORTH,
797 .channels = 1,
798 .buswidth = 4,
799 .num_links = 0,
800};
801
802static struct qcom_icc_node qhs_camera_cfg = {
803 .name = "qhs_camera_cfg",
804 .id = SC7280_SLAVE_CAMERA_CFG,
805 .channels = 1,
806 .buswidth = 4,
807 .num_links = 0,
808};
809
810static struct qcom_icc_node qhs_clk_ctl = {
811 .name = "qhs_clk_ctl",
812 .id = SC7280_SLAVE_CLK_CTL,
813 .channels = 1,
814 .buswidth = 4,
815 .num_links = 0,
816};
817
818static struct qcom_icc_node qhs_compute_cfg = {
819 .name = "qhs_compute_cfg",
820 .id = SC7280_SLAVE_CDSP_CFG,
821 .channels = 1,
822 .buswidth = 4,
823 .num_links = 1,
824 .links = { SC7280_MASTER_CDSP_NOC_CFG },
825};
826
827static struct qcom_icc_node qhs_cpr_cx = {
828 .name = "qhs_cpr_cx",
829 .id = SC7280_SLAVE_RBCPR_CX_CFG,
830 .channels = 1,
831 .buswidth = 4,
832 .num_links = 0,
833};
834
835static struct qcom_icc_node qhs_cpr_mx = {
836 .name = "qhs_cpr_mx",
837 .id = SC7280_SLAVE_RBCPR_MX_CFG,
838 .channels = 1,
839 .buswidth = 4,
840 .num_links = 0,
841};
842
843static struct qcom_icc_node qhs_crypto0_cfg = {
844 .name = "qhs_crypto0_cfg",
845 .id = SC7280_SLAVE_CRYPTO_0_CFG,
846 .channels = 1,
847 .buswidth = 4,
848 .num_links = 0,
849};
850
851static struct qcom_icc_node qhs_cx_rdpm = {
852 .name = "qhs_cx_rdpm",
853 .id = SC7280_SLAVE_CX_RDPM,
854 .channels = 1,
855 .buswidth = 4,
856 .num_links = 0,
857};
858
859static struct qcom_icc_node qhs_dcc_cfg = {
860 .name = "qhs_dcc_cfg",
861 .id = SC7280_SLAVE_DCC_CFG,
862 .channels = 1,
863 .buswidth = 4,
864 .num_links = 0,
865};
866
867static struct qcom_icc_node qhs_display_cfg = {
868 .name = "qhs_display_cfg",
869 .id = SC7280_SLAVE_DISPLAY_CFG,
870 .channels = 1,
871 .buswidth = 4,
872 .num_links = 0,
873};
874
875static struct qcom_icc_node qhs_gpuss_cfg = {
876 .name = "qhs_gpuss_cfg",
877 .id = SC7280_SLAVE_GFX3D_CFG,
878 .channels = 1,
879 .buswidth = 8,
880 .num_links = 0,
881};
882
883static struct qcom_icc_node qhs_hwkm = {
884 .name = "qhs_hwkm",
885 .id = SC7280_SLAVE_HWKM,
886 .channels = 1,
887 .buswidth = 4,
888 .num_links = 0,
889};
890
891static struct qcom_icc_node qhs_imem_cfg = {
892 .name = "qhs_imem_cfg",
893 .id = SC7280_SLAVE_IMEM_CFG,
894 .channels = 1,
895 .buswidth = 4,
896 .num_links = 0,
897};
898
899static struct qcom_icc_node qhs_ipa = {
900 .name = "qhs_ipa",
901 .id = SC7280_SLAVE_IPA_CFG,
902 .channels = 1,
903 .buswidth = 4,
904 .num_links = 0,
905};
906
907static struct qcom_icc_node qhs_ipc_router = {
908 .name = "qhs_ipc_router",
909 .id = SC7280_SLAVE_IPC_ROUTER_CFG,
910 .channels = 1,
911 .buswidth = 4,
912 .num_links = 0,
913};
914
915static struct qcom_icc_node qhs_lpass_cfg = {
916 .name = "qhs_lpass_cfg",
917 .id = SC7280_SLAVE_LPASS,
918 .channels = 1,
919 .buswidth = 4,
920 .num_links = 1,
921 .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
922};
923
924static struct qcom_icc_node qhs_mss_cfg = {
925 .name = "qhs_mss_cfg",
926 .id = SC7280_SLAVE_CNOC_MSS,
927 .channels = 1,
928 .buswidth = 4,
929 .num_links = 0,
930};
931
932static struct qcom_icc_node qhs_mx_rdpm = {
933 .name = "qhs_mx_rdpm",
934 .id = SC7280_SLAVE_MX_RDPM,
935 .channels = 1,
936 .buswidth = 4,
937 .num_links = 0,
938};
939
940static struct qcom_icc_node qhs_pcie0_cfg = {
941 .name = "qhs_pcie0_cfg",
942 .id = SC7280_SLAVE_PCIE_0_CFG,
943 .channels = 1,
944 .buswidth = 4,
945 .num_links = 0,
946};
947
948static struct qcom_icc_node qhs_pcie1_cfg = {
949 .name = "qhs_pcie1_cfg",
950 .id = SC7280_SLAVE_PCIE_1_CFG,
951 .channels = 1,
952 .buswidth = 4,
953 .num_links = 0,
954};
955
956static struct qcom_icc_node qhs_pdm = {
957 .name = "qhs_pdm",
958 .id = SC7280_SLAVE_PDM,
959 .channels = 1,
960 .buswidth = 4,
961 .num_links = 0,
962};
963
964static struct qcom_icc_node qhs_pimem_cfg = {
965 .name = "qhs_pimem_cfg",
966 .id = SC7280_SLAVE_PIMEM_CFG,
967 .channels = 1,
968 .buswidth = 4,
969 .num_links = 0,
970};
971
972static struct qcom_icc_node qhs_pka_wrapper_cfg = {
973 .name = "qhs_pka_wrapper_cfg",
974 .id = SC7280_SLAVE_PKA_WRAPPER_CFG,
975 .channels = 1,
976 .buswidth = 4,
977 .num_links = 0,
978};
979
980static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
981 .name = "qhs_pmu_wrapper_cfg",
982 .id = SC7280_SLAVE_PMU_WRAPPER_CFG,
983 .channels = 1,
984 .buswidth = 4,
985 .num_links = 0,
986};
987
988static struct qcom_icc_node qhs_qdss_cfg = {
989 .name = "qhs_qdss_cfg",
990 .id = SC7280_SLAVE_QDSS_CFG,
991 .channels = 1,
992 .buswidth = 4,
993 .num_links = 0,
994};
995
996static struct qcom_icc_node qhs_qspi = {
997 .name = "qhs_qspi",
998 .id = SC7280_SLAVE_QSPI_0,
999 .channels = 1,
1000 .buswidth = 4,
1001 .num_links = 0,
1002};
1003
1004static struct qcom_icc_node qhs_qup0 = {
1005 .name = "qhs_qup0",
1006 .id = SC7280_SLAVE_QUP_0,
1007 .channels = 1,
1008 .buswidth = 4,
1009 .num_links = 0,
1010};
1011
1012static struct qcom_icc_node qhs_qup1 = {
1013 .name = "qhs_qup1",
1014 .id = SC7280_SLAVE_QUP_1,
1015 .channels = 1,
1016 .buswidth = 4,
1017 .num_links = 0,
1018};
1019
1020static struct qcom_icc_node qhs_sdc1 = {
1021 .name = "qhs_sdc1",
1022 .id = SC7280_SLAVE_SDCC_1,
1023 .channels = 1,
1024 .buswidth = 4,
1025 .num_links = 0,
1026};
1027
1028static struct qcom_icc_node qhs_sdc2 = {
1029 .name = "qhs_sdc2",
1030 .id = SC7280_SLAVE_SDCC_2,
1031 .channels = 1,
1032 .buswidth = 4,
1033 .num_links = 0,
1034};
1035
1036static struct qcom_icc_node qhs_sdc4 = {
1037 .name = "qhs_sdc4",
1038 .id = SC7280_SLAVE_SDCC_4,
1039 .channels = 1,
1040 .buswidth = 4,
1041 .num_links = 0,
1042};
1043
1044static struct qcom_icc_node qhs_security = {
1045 .name = "qhs_security",
1046 .id = SC7280_SLAVE_SECURITY,
1047 .channels = 1,
1048 .buswidth = 4,
1049 .num_links = 0,
1050};
1051
1052static struct qcom_icc_node qhs_tcsr = {
1053 .name = "qhs_tcsr",
1054 .id = SC7280_SLAVE_TCSR,
1055 .channels = 1,
1056 .buswidth = 4,
1057 .num_links = 0,
1058};
1059
1060static struct qcom_icc_node qhs_tlmm = {
1061 .name = "qhs_tlmm",
1062 .id = SC7280_SLAVE_TLMM,
1063 .channels = 1,
1064 .buswidth = 4,
1065 .num_links = 0,
1066};
1067
1068static struct qcom_icc_node qhs_ufs_mem_cfg = {
1069 .name = "qhs_ufs_mem_cfg",
1070 .id = SC7280_SLAVE_UFS_MEM_CFG,
1071 .channels = 1,
1072 .buswidth = 4,
1073 .num_links = 0,
1074};
1075
1076static struct qcom_icc_node qhs_usb2 = {
1077 .name = "qhs_usb2",
1078 .id = SC7280_SLAVE_USB2,
1079 .channels = 1,
1080 .buswidth = 4,
1081 .num_links = 0,
1082};
1083
1084static struct qcom_icc_node qhs_usb3_0 = {
1085 .name = "qhs_usb3_0",
1086 .id = SC7280_SLAVE_USB3_0,
1087 .channels = 1,
1088 .buswidth = 4,
1089 .num_links = 0,
1090};
1091
1092static struct qcom_icc_node qhs_venus_cfg = {
1093 .name = "qhs_venus_cfg",
1094 .id = SC7280_SLAVE_VENUS_CFG,
1095 .channels = 1,
1096 .buswidth = 4,
1097 .num_links = 0,
1098};
1099
1100static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1101 .name = "qhs_vsense_ctrl_cfg",
1102 .id = SC7280_SLAVE_VSENSE_CTRL_CFG,
1103 .channels = 1,
1104 .buswidth = 4,
1105 .num_links = 0,
1106};
1107
1108static struct qcom_icc_node qns_a1_noc_cfg = {
1109 .name = "qns_a1_noc_cfg",
1110 .id = SC7280_SLAVE_A1NOC_CFG,
1111 .channels = 1,
1112 .buswidth = 4,
1113 .num_links = 1,
1114 .links = { SC7280_MASTER_A1NOC_CFG },
1115};
1116
1117static struct qcom_icc_node qns_a2_noc_cfg = {
1118 .name = "qns_a2_noc_cfg",
1119 .id = SC7280_SLAVE_A2NOC_CFG,
1120 .channels = 1,
1121 .buswidth = 4,
1122 .num_links = 1,
1123 .links = { SC7280_MASTER_A2NOC_CFG },
1124};
1125
1126static struct qcom_icc_node qns_cnoc2_cnoc3 = {
1127 .name = "qns_cnoc2_cnoc3",
1128 .id = SC7280_SLAVE_CNOC2_CNOC3,
1129 .channels = 1,
1130 .buswidth = 8,
1131 .num_links = 1,
1132 .links = { SC7280_MASTER_CNOC2_CNOC3 },
1133};
1134
1135static struct qcom_icc_node qns_mnoc_cfg = {
1136 .name = "qns_mnoc_cfg",
1137 .id = SC7280_SLAVE_CNOC_MNOC_CFG,
1138 .channels = 1,
1139 .buswidth = 4,
1140 .num_links = 1,
1141 .links = { SC7280_MASTER_CNOC_MNOC_CFG },
1142};
1143
1144static struct qcom_icc_node qns_snoc_cfg = {
1145 .name = "qns_snoc_cfg",
1146 .id = SC7280_SLAVE_SNOC_CFG,
1147 .channels = 1,
1148 .buswidth = 4,
1149 .num_links = 1,
1150 .links = { SC7280_MASTER_SNOC_CFG },
1151};
1152
1153static struct qcom_icc_node qhs_aoss = {
1154 .name = "qhs_aoss",
1155 .id = SC7280_SLAVE_AOSS,
1156 .channels = 1,
1157 .buswidth = 4,
1158 .num_links = 0,
1159};
1160
1161static struct qcom_icc_node qhs_apss = {
1162 .name = "qhs_apss",
1163 .id = SC7280_SLAVE_APPSS,
1164 .channels = 1,
1165 .buswidth = 8,
1166 .num_links = 0,
1167};
1168
1169static struct qcom_icc_node qns_cnoc3_cnoc2 = {
1170 .name = "qns_cnoc3_cnoc2",
1171 .id = SC7280_SLAVE_CNOC3_CNOC2,
1172 .channels = 1,
1173 .buswidth = 8,
1174 .num_links = 1,
1175 .links = { SC7280_MASTER_CNOC3_CNOC2 },
1176};
1177
1178static struct qcom_icc_node qns_cnoc_a2noc = {
1179 .name = "qns_cnoc_a2noc",
1180 .id = SC7280_SLAVE_CNOC_A2NOC,
1181 .channels = 1,
1182 .buswidth = 8,
1183 .num_links = 1,
1184 .links = { SC7280_MASTER_CNOC_A2NOC },
1185};
1186
1187static struct qcom_icc_node qns_ddrss_cfg = {
1188 .name = "qns_ddrss_cfg",
1189 .id = SC7280_SLAVE_DDRSS_CFG,
1190 .channels = 1,
1191 .buswidth = 4,
1192 .num_links = 1,
1193 .links = { SC7280_MASTER_CNOC_DC_NOC },
1194};
1195
1196static struct qcom_icc_node qxs_boot_imem = {
1197 .name = "qxs_boot_imem",
1198 .id = SC7280_SLAVE_BOOT_IMEM,
1199 .channels = 1,
1200 .buswidth = 8,
1201 .num_links = 0,
1202};
1203
1204static struct qcom_icc_node qxs_imem = {
1205 .name = "qxs_imem",
1206 .id = SC7280_SLAVE_IMEM,
1207 .channels = 1,
1208 .buswidth = 8,
1209 .num_links = 0,
1210};
1211
1212static struct qcom_icc_node qxs_pimem = {
1213 .name = "qxs_pimem",
1214 .id = SC7280_SLAVE_PIMEM,
1215 .channels = 1,
1216 .buswidth = 8,
1217 .num_links = 0,
1218};
1219
1220static struct qcom_icc_node xs_pcie_0 = {
1221 .name = "xs_pcie_0",
1222 .id = SC7280_SLAVE_PCIE_0,
1223 .channels = 1,
1224 .buswidth = 8,
1225 .num_links = 0,
1226};
1227
1228static struct qcom_icc_node xs_pcie_1 = {
1229 .name = "xs_pcie_1",
1230 .id = SC7280_SLAVE_PCIE_1,
1231 .channels = 1,
1232 .buswidth = 8,
1233 .num_links = 0,
1234};
1235
1236static struct qcom_icc_node xs_qdss_stm = {
1237 .name = "xs_qdss_stm",
1238 .id = SC7280_SLAVE_QDSS_STM,
1239 .channels = 1,
1240 .buswidth = 4,
1241 .num_links = 0,
1242};
1243
1244static struct qcom_icc_node xs_sys_tcu_cfg = {
1245 .name = "xs_sys_tcu_cfg",
1246 .id = SC7280_SLAVE_TCU,
1247 .channels = 1,
1248 .buswidth = 8,
1249 .num_links = 0,
1250};
1251
1252static struct qcom_icc_node qhs_llcc = {
1253 .name = "qhs_llcc",
1254 .id = SC7280_SLAVE_LLCC_CFG,
1255 .channels = 1,
1256 .buswidth = 4,
1257 .num_links = 0,
1258};
1259
1260static struct qcom_icc_node qns_gemnoc = {
1261 .name = "qns_gemnoc",
1262 .id = SC7280_SLAVE_GEM_NOC_CFG,
1263 .channels = 1,
1264 .buswidth = 4,
1265 .num_links = 1,
1266 .links = { SC7280_MASTER_GEM_NOC_CFG },
1267};
1268
1269static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1270 .name = "qhs_mdsp_ms_mpu_cfg",
1271 .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
1272 .channels = 1,
1273 .buswidth = 4,
1274 .num_links = 0,
1275};
1276
1277static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1278 .name = "qhs_modem_ms_mpu_cfg",
1279 .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
1280 .channels = 1,
1281 .buswidth = 4,
1282 .num_links = 0,
1283};
1284
1285static struct qcom_icc_node qns_gem_noc_cnoc = {
1286 .name = "qns_gem_noc_cnoc",
1287 .id = SC7280_SLAVE_GEM_NOC_CNOC,
1288 .channels = 1,
1289 .buswidth = 16,
1290 .num_links = 1,
1291 .links = { SC7280_MASTER_GEM_NOC_CNOC },
1292};
1293
1294static struct qcom_icc_node qns_llcc = {
1295 .name = "qns_llcc",
1296 .id = SC7280_SLAVE_LLCC,
1297 .channels = 2,
1298 .buswidth = 16,
1299 .num_links = 1,
1300 .links = { SC7280_MASTER_LLCC },
1301};
1302
1303static struct qcom_icc_node qns_pcie = {
1304 .name = "qns_pcie",
1305 .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
1306 .channels = 1,
1307 .buswidth = 8,
1308 .num_links = 1,
1309 .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
1310};
1311
1312static struct qcom_icc_node srvc_even_gemnoc = {
1313 .name = "srvc_even_gemnoc",
1314 .id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
1315 .channels = 1,
1316 .buswidth = 4,
1317 .num_links = 0,
1318};
1319
1320static struct qcom_icc_node srvc_odd_gemnoc = {
1321 .name = "srvc_odd_gemnoc",
1322 .id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
1323 .channels = 1,
1324 .buswidth = 4,
1325 .num_links = 0,
1326};
1327
1328static struct qcom_icc_node srvc_sys_gemnoc = {
1329 .name = "srvc_sys_gemnoc",
1330 .id = SC7280_SLAVE_SERVICE_GEM_NOC,
1331 .channels = 1,
1332 .buswidth = 4,
1333 .num_links = 0,
1334};
1335
1336static struct qcom_icc_node qhs_lpass_core = {
1337 .name = "qhs_lpass_core",
1338 .id = SC7280_SLAVE_LPASS_CORE_CFG,
1339 .channels = 1,
1340 .buswidth = 4,
1341 .num_links = 0,
1342};
1343
1344static struct qcom_icc_node qhs_lpass_lpi = {
1345 .name = "qhs_lpass_lpi",
1346 .id = SC7280_SLAVE_LPASS_LPI_CFG,
1347 .channels = 1,
1348 .buswidth = 4,
1349 .num_links = 0,
1350};
1351
1352static struct qcom_icc_node qhs_lpass_mpu = {
1353 .name = "qhs_lpass_mpu",
1354 .id = SC7280_SLAVE_LPASS_MPU_CFG,
1355 .channels = 1,
1356 .buswidth = 4,
1357 .num_links = 0,
1358};
1359
1360static struct qcom_icc_node qhs_lpass_top = {
1361 .name = "qhs_lpass_top",
1362 .id = SC7280_SLAVE_LPASS_TOP_CFG,
1363 .channels = 1,
1364 .buswidth = 4,
1365 .num_links = 0,
1366};
1367
1368static struct qcom_icc_node srvc_niu_aml_noc = {
1369 .name = "srvc_niu_aml_noc",
1370 .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
1371 .channels = 1,
1372 .buswidth = 4,
1373 .num_links = 0,
1374};
1375
1376static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1377 .name = "srvc_niu_lpass_agnoc",
1378 .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
1379 .channels = 1,
1380 .buswidth = 4,
1381 .num_links = 0,
1382};
1383
1384static struct qcom_icc_node ebi = {
1385 .name = "ebi",
1386 .id = SC7280_SLAVE_EBI1,
1387 .channels = 2,
1388 .buswidth = 4,
1389 .num_links = 0,
1390};
1391
1392static struct qcom_icc_node qns_mem_noc_hf = {
1393 .name = "qns_mem_noc_hf",
1394 .id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
1395 .channels = 2,
1396 .buswidth = 32,
1397 .num_links = 1,
1398 .links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
1399};
1400
1401static struct qcom_icc_node qns_mem_noc_sf = {
1402 .name = "qns_mem_noc_sf",
1403 .id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
1404 .channels = 1,
1405 .buswidth = 32,
1406 .num_links = 1,
1407 .links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
1408};
1409
1410static struct qcom_icc_node srvc_mnoc = {
1411 .name = "srvc_mnoc",
1412 .id = SC7280_SLAVE_SERVICE_MNOC,
1413 .channels = 1,
1414 .buswidth = 4,
1415 .num_links = 0,
1416};
1417
1418static struct qcom_icc_node qns_nsp_gemnoc = {
1419 .name = "qns_nsp_gemnoc",
1420 .id = SC7280_SLAVE_CDSP_MEM_NOC,
1421 .channels = 2,
1422 .buswidth = 32,
1423 .num_links = 1,
1424 .links = { SC7280_MASTER_COMPUTE_NOC },
1425};
1426
1427static struct qcom_icc_node service_nsp_noc = {
1428 .name = "service_nsp_noc",
1429 .id = SC7280_SLAVE_SERVICE_NSP_NOC,
1430 .channels = 1,
1431 .buswidth = 4,
1432 .num_links = 0,
1433};
1434
1435static struct qcom_icc_node qns_gemnoc_gc = {
1436 .name = "qns_gemnoc_gc",
1437 .id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
1438 .channels = 1,
1439 .buswidth = 8,
1440 .num_links = 1,
1441 .links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
1442};
1443
1444static struct qcom_icc_node qns_gemnoc_sf = {
1445 .name = "qns_gemnoc_sf",
1446 .id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
1447 .channels = 1,
1448 .buswidth = 16,
1449 .num_links = 1,
1450 .links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
1451};
1452
1453static struct qcom_icc_node srvc_snoc = {
1454 .name = "srvc_snoc",
1455 .id = SC7280_SLAVE_SERVICE_SNOC,
1456 .channels = 1,
1457 .buswidth = 4,
1458 .num_links = 0,
1459};
1460
1461static struct qcom_icc_bcm bcm_acv = {
1462 .name = "ACV",
1463 .enable_mask = BIT(3),
1464 .num_nodes = 1,
1465 .nodes = { &ebi },
1466};
1467
1468static struct qcom_icc_bcm bcm_ce0 = {
1469 .name = "CE0",
1470 .num_nodes = 1,
1471 .nodes = { &qxm_crypto },
1472};
1473
1474static struct qcom_icc_bcm bcm_cn0 = {
1475 .name = "CN0",
1476 .keepalive = true,
1477 .num_nodes = 2,
1478 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1479};
1480
1481static struct qcom_icc_bcm bcm_cn1 = {
1482 .name = "CN1",
1483 .num_nodes = 47,
1484 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
1485 &qhs_ahb2phy0, &qhs_ahb2phy1,
1486 &qhs_camera_cfg, &qhs_clk_ctl,
1487 &qhs_compute_cfg, &qhs_cpr_cx,
1488 &qhs_cpr_mx, &qhs_crypto0_cfg,
1489 &qhs_cx_rdpm, &qhs_dcc_cfg,
1490 &qhs_display_cfg, &qhs_gpuss_cfg,
1491 &qhs_hwkm, &qhs_imem_cfg,
1492 &qhs_ipa, &qhs_ipc_router,
1493 &qhs_mss_cfg, &qhs_mx_rdpm,
1494 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1495 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
1496 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
1497 &qhs_qup0, &qhs_qup1,
1498 &qhs_security, &qhs_tcsr,
1499 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2,
1500 &qhs_usb3_0, &qhs_venus_cfg,
1501 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
1502 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3,
1503 &qns_mnoc_cfg, &qns_snoc_cfg,
1504 &qnm_cnoc2_cnoc3, &qhs_aoss,
1505 &qhs_apss, &qns_cnoc3_cnoc2,
1506 &qns_cnoc_a2noc, &qns_ddrss_cfg },
1507};
1508
1509static struct qcom_icc_bcm bcm_cn2 = {
1510 .name = "CN2",
1511 .num_nodes = 6,
1512 .nodes = { &qhs_lpass_cfg, &qhs_pdm,
1513 &qhs_qspi, &qhs_sdc1,
1514 &qhs_sdc2, &qhs_sdc4 },
1515};
1516
1517static struct qcom_icc_bcm bcm_co0 = {
1518 .name = "CO0",
1519 .num_nodes = 1,
1520 .nodes = { &qns_nsp_gemnoc },
1521};
1522
1523static struct qcom_icc_bcm bcm_co3 = {
1524 .name = "CO3",
1525 .num_nodes = 1,
1526 .nodes = { &qxm_nsp },
1527};
1528
1529static struct qcom_icc_bcm bcm_mc0 = {
1530 .name = "MC0",
1531 .keepalive = true,
1532 .num_nodes = 1,
1533 .nodes = { &ebi },
1534};
1535
1536static struct qcom_icc_bcm bcm_mm0 = {
1537 .name = "MM0",
1538 .keepalive = true,
1539 .num_nodes = 1,
1540 .nodes = { &qns_mem_noc_hf },
1541};
1542
1543static struct qcom_icc_bcm bcm_mm1 = {
1544 .name = "MM1",
1545 .num_nodes = 2,
1546 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
1547};
1548
1549static struct qcom_icc_bcm bcm_mm4 = {
1550 .name = "MM4",
1551 .num_nodes = 1,
1552 .nodes = { &qns_mem_noc_sf },
1553};
1554
1555static struct qcom_icc_bcm bcm_mm5 = {
1556 .name = "MM5",
1557 .num_nodes = 3,
1558 .nodes = { &qnm_video0, &qxm_camnoc_icp,
1559 &qxm_camnoc_sf },
1560};
1561
1562static struct qcom_icc_bcm bcm_qup0 = {
1563 .name = "QUP0",
1564 .vote_scale = 1,
1565 .num_nodes = 1,
1566 .nodes = { &qup0_core_slave },
1567};
1568
1569static struct qcom_icc_bcm bcm_qup1 = {
1570 .name = "QUP1",
1571 .vote_scale = 1,
1572 .num_nodes = 1,
1573 .nodes = { &qup1_core_slave },
1574};
1575
1576static struct qcom_icc_bcm bcm_sh0 = {
1577 .name = "SH0",
1578 .keepalive = true,
1579 .num_nodes = 1,
1580 .nodes = { &qns_llcc },
1581};
1582
1583static struct qcom_icc_bcm bcm_sh2 = {
1584 .name = "SH2",
1585 .num_nodes = 2,
1586 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1587};
1588
1589static struct qcom_icc_bcm bcm_sh3 = {
1590 .name = "SH3",
1591 .num_nodes = 1,
1592 .nodes = { &qnm_cmpnoc },
1593};
1594
1595static struct qcom_icc_bcm bcm_sh4 = {
1596 .name = "SH4",
1597 .num_nodes = 1,
1598 .nodes = { &chm_apps },
1599};
1600
1601static struct qcom_icc_bcm bcm_sn0 = {
1602 .name = "SN0",
1603 .keepalive = true,
1604 .num_nodes = 1,
1605 .nodes = { &qns_gemnoc_sf },
1606};
1607
1608static struct qcom_icc_bcm bcm_sn2 = {
1609 .name = "SN2",
1610 .num_nodes = 1,
1611 .nodes = { &qns_gemnoc_gc },
1612};
1613
1614static struct qcom_icc_bcm bcm_sn3 = {
1615 .name = "SN3",
1616 .num_nodes = 1,
1617 .nodes = { &qxs_pimem },
1618};
1619
1620static struct qcom_icc_bcm bcm_sn4 = {
1621 .name = "SN4",
1622 .num_nodes = 1,
1623 .nodes = { &xs_qdss_stm },
1624};
1625
1626static struct qcom_icc_bcm bcm_sn5 = {
1627 .name = "SN5",
1628 .num_nodes = 1,
1629 .nodes = { &xm_pcie3_0 },
1630};
1631
1632static struct qcom_icc_bcm bcm_sn6 = {
1633 .name = "SN6",
1634 .num_nodes = 1,
1635 .nodes = { &xm_pcie3_1 },
1636};
1637
1638static struct qcom_icc_bcm bcm_sn7 = {
1639 .name = "SN7",
1640 .num_nodes = 1,
1641 .nodes = { &qnm_aggre1_noc },
1642};
1643
1644static struct qcom_icc_bcm bcm_sn8 = {
1645 .name = "SN8",
1646 .num_nodes = 1,
1647 .nodes = { &qnm_aggre2_noc },
1648};
1649
1650static struct qcom_icc_bcm bcm_sn14 = {
1651 .name = "SN14",
1652 .num_nodes = 1,
1653 .nodes = { &qns_pcie_mem_noc },
1654};
1655
1656static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1657 &bcm_sn5,
1658 &bcm_sn6,
1659 &bcm_sn14,
1660};
1661
1662static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1663 [MASTER_QSPI_0] = &qhm_qspi,
1664 [MASTER_QUP_0] = &qhm_qup0,
1665 [MASTER_QUP_1] = &qhm_qup1,
1666 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1667 [MASTER_PCIE_0] = &xm_pcie3_0,
1668 [MASTER_PCIE_1] = &xm_pcie3_1,
1669 [MASTER_SDCC_1] = &xm_sdc1,
1670 [MASTER_SDCC_2] = &xm_sdc2,
1671 [MASTER_SDCC_4] = &xm_sdc4,
1672 [MASTER_UFS_MEM] = &xm_ufs_mem,
1673 [MASTER_USB2] = &xm_usb2,
1674 [MASTER_USB3_0] = &xm_usb3_0,
1675 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1676 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1677 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1678};
1679
1680static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
1681 .reg_bits = 32,
1682 .reg_stride = 4,
1683 .val_bits = 32,
1684 .max_register = 0x1c080,
1685 .fast_io = true,
1686};
1687
1688static const struct qcom_icc_desc sc7280_aggre1_noc = {
1689 .config = &sc7280_aggre1_noc_regmap_config,
1690 .nodes = aggre1_noc_nodes,
1691 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1692 .bcms = aggre1_noc_bcms,
1693 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1694 .qos_requires_clocks = true,
1695};
1696
1697static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1698 &bcm_ce0,
1699};
1700
1701static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
1702 .reg_bits = 32,
1703 .reg_stride = 4,
1704 .val_bits = 32,
1705 .max_register = 0x2b080,
1706 .fast_io = true,
1707};
1708
1709static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1710 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1711 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1712 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1713 [MASTER_CRYPTO] = &qxm_crypto,
1714 [MASTER_IPA] = &qxm_ipa,
1715 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1716 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1717 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1718};
1719
1720static const struct qcom_icc_desc sc7280_aggre2_noc = {
1721 .config = &sc7280_aggre2_noc_regmap_config,
1722 .nodes = aggre2_noc_nodes,
1723 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1724 .bcms = aggre2_noc_bcms,
1725 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1726 .qos_requires_clocks = true,
1727};
1728
1729static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1730 &bcm_qup0,
1731 &bcm_qup1,
1732};
1733
1734static struct qcom_icc_node * const clk_virt_nodes[] = {
1735 [MASTER_QUP_CORE_0] = &qup0_core_master,
1736 [MASTER_QUP_CORE_1] = &qup1_core_master,
1737 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1738 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1739};
1740
1741static const struct qcom_icc_desc sc7280_clk_virt = {
1742 .nodes = clk_virt_nodes,
1743 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1744 .bcms = clk_virt_bcms,
1745 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1746};
1747
1748static struct qcom_icc_bcm * const cnoc2_bcms[] = {
1749 &bcm_cn1,
1750 &bcm_cn2,
1751};
1752
1753static struct qcom_icc_node * const cnoc2_nodes[] = {
1754 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
1755 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1756 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1757 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1758 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1759 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1760 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1761 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1762 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1763 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1764 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1765 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1766 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1767 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1768 [SLAVE_HWKM] = &qhs_hwkm,
1769 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1770 [SLAVE_IPA_CFG] = &qhs_ipa,
1771 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1772 [SLAVE_LPASS] = &qhs_lpass_cfg,
1773 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1774 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1775 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1776 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1777 [SLAVE_PDM] = &qhs_pdm,
1778 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1779 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1780 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1781 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1782 [SLAVE_QSPI_0] = &qhs_qspi,
1783 [SLAVE_QUP_0] = &qhs_qup0,
1784 [SLAVE_QUP_1] = &qhs_qup1,
1785 [SLAVE_SDCC_1] = &qhs_sdc1,
1786 [SLAVE_SDCC_2] = &qhs_sdc2,
1787 [SLAVE_SDCC_4] = &qhs_sdc4,
1788 [SLAVE_SECURITY] = &qhs_security,
1789 [SLAVE_TCSR] = &qhs_tcsr,
1790 [SLAVE_TLMM] = &qhs_tlmm,
1791 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1792 [SLAVE_USB2] = &qhs_usb2,
1793 [SLAVE_USB3_0] = &qhs_usb3_0,
1794 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1795 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1796 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1797 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1798 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3,
1799 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1800 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1801};
1802
1803static const struct regmap_config sc7280_cnoc2_regmap_config = {
1804 .reg_bits = 32,
1805 .reg_stride = 4,
1806 .val_bits = 32,
1807 .max_register = 0x1000,
1808 .fast_io = true,
1809};
1810
1811static const struct qcom_icc_desc sc7280_cnoc2 = {
1812 .config = &sc7280_cnoc2_regmap_config,
1813 .nodes = cnoc2_nodes,
1814 .num_nodes = ARRAY_SIZE(cnoc2_nodes),
1815 .bcms = cnoc2_bcms,
1816 .num_bcms = ARRAY_SIZE(cnoc2_bcms),
1817};
1818
1819static struct qcom_icc_bcm * const cnoc3_bcms[] = {
1820 &bcm_cn0,
1821 &bcm_cn1,
1822 &bcm_sn3,
1823 &bcm_sn4,
1824};
1825
1826static struct qcom_icc_node * const cnoc3_nodes[] = {
1827 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
1828 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1829 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1830 [SLAVE_AOSS] = &qhs_aoss,
1831 [SLAVE_APPSS] = &qhs_apss,
1832 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2,
1833 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1834 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1835 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1836 [SLAVE_IMEM] = &qxs_imem,
1837 [SLAVE_PIMEM] = &qxs_pimem,
1838 [SLAVE_PCIE_0] = &xs_pcie_0,
1839 [SLAVE_PCIE_1] = &xs_pcie_1,
1840 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1841 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1842};
1843
1844static const struct regmap_config sc7280_cnoc3_regmap_config = {
1845 .reg_bits = 32,
1846 .reg_stride = 4,
1847 .val_bits = 32,
1848 .max_register = 0x1000,
1849 .fast_io = true,
1850};
1851
1852static const struct qcom_icc_desc sc7280_cnoc3 = {
1853 .config = &sc7280_cnoc3_regmap_config,
1854 .nodes = cnoc3_nodes,
1855 .num_nodes = ARRAY_SIZE(cnoc3_nodes),
1856 .bcms = cnoc3_bcms,
1857 .num_bcms = ARRAY_SIZE(cnoc3_bcms),
1858};
1859
1860static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1861};
1862
1863static struct qcom_icc_node * const dc_noc_nodes[] = {
1864 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1865 [SLAVE_LLCC_CFG] = &qhs_llcc,
1866 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1867};
1868
1869static const struct regmap_config sc7280_dc_noc_regmap_config = {
1870 .reg_bits = 32,
1871 .reg_stride = 4,
1872 .val_bits = 32,
1873 .max_register = 0x5080,
1874 .fast_io = true,
1875};
1876
1877static const struct qcom_icc_desc sc7280_dc_noc = {
1878 .config = &sc7280_dc_noc_regmap_config,
1879 .nodes = dc_noc_nodes,
1880 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1881 .bcms = dc_noc_bcms,
1882 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1883};
1884
1885static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1886 &bcm_sh0,
1887 &bcm_sh2,
1888 &bcm_sh3,
1889 &bcm_sh4,
1890};
1891
1892static struct qcom_icc_node * const gem_noc_nodes[] = {
1893 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1894 [MASTER_SYS_TCU] = &alm_sys_tcu,
1895 [MASTER_APPSS_PROC] = &chm_apps,
1896 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1897 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1898 [MASTER_GFX3D] = &qnm_gpu,
1899 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1900 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1901 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1902 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1903 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1904 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1905 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1906 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1907 [SLAVE_LLCC] = &qns_llcc,
1908 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1909 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1910 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1911 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1912};
1913
1914static const struct regmap_config sc7280_gem_noc_regmap_config = {
1915 .reg_bits = 32,
1916 .reg_stride = 4,
1917 .val_bits = 32,
1918 .max_register = 0xe2200,
1919 .fast_io = true,
1920};
1921
1922static const struct qcom_icc_desc sc7280_gem_noc = {
1923 .config = &sc7280_gem_noc_regmap_config,
1924 .nodes = gem_noc_nodes,
1925 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1926 .bcms = gem_noc_bcms,
1927 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1928};
1929
1930static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1931};
1932
1933static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1934 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1935 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1936 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1937 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1938 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1939 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1940 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1941};
1942
1943static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
1944 .reg_bits = 32,
1945 .reg_stride = 4,
1946 .val_bits = 32,
1947 .max_register = 0xf080,
1948 .fast_io = true,
1949};
1950
1951static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1952 .config = &sc7280_lpass_ag_noc_regmap_config,
1953 .nodes = lpass_ag_noc_nodes,
1954 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1955 .bcms = lpass_ag_noc_bcms,
1956 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1957};
1958
1959static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1960 &bcm_acv,
1961 &bcm_mc0,
1962};
1963
1964static struct qcom_icc_node * const mc_virt_nodes[] = {
1965 [MASTER_LLCC] = &llcc_mc,
1966 [SLAVE_EBI1] = &ebi,
1967};
1968
1969static const struct regmap_config sc7280_mc_virt_regmap_config = {
1970 .reg_bits = 32,
1971 .reg_stride = 4,
1972 .val_bits = 32,
1973 .max_register = 0x4,
1974 .fast_io = true,
1975};
1976
1977static const struct qcom_icc_desc sc7280_mc_virt = {
1978 .config = &sc7280_mc_virt_regmap_config,
1979 .nodes = mc_virt_nodes,
1980 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1981 .bcms = mc_virt_bcms,
1982 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1983};
1984
1985static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1986 &bcm_mm0,
1987 &bcm_mm1,
1988 &bcm_mm4,
1989 &bcm_mm5,
1990};
1991
1992static struct qcom_icc_node * const mmss_noc_nodes[] = {
1993 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1994 [MASTER_VIDEO_P0] = &qnm_video0,
1995 [MASTER_VIDEO_PROC] = &qnm_video_cpu,
1996 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
1997 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
1998 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1999 [MASTER_MDP0] = &qxm_mdp0,
2000 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2001 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2002 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2003};
2004
2005static const struct regmap_config sc7280_mmss_noc_regmap_config = {
2006 .reg_bits = 32,
2007 .reg_stride = 4,
2008 .val_bits = 32,
2009 .max_register = 0x1e080,
2010 .fast_io = true,
2011};
2012
2013static const struct qcom_icc_desc sc7280_mmss_noc = {
2014 .config = &sc7280_mmss_noc_regmap_config,
2015 .nodes = mmss_noc_nodes,
2016 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2017 .bcms = mmss_noc_bcms,
2018 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2019};
2020
2021static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
2022 &bcm_co0,
2023 &bcm_co3,
2024};
2025
2026static struct qcom_icc_node * const nsp_noc_nodes[] = {
2027 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2028 [MASTER_CDSP_PROC] = &qxm_nsp,
2029 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2030 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2031};
2032
2033static const struct regmap_config sc7280_nsp_noc_regmap_config = {
2034 .reg_bits = 32,
2035 .reg_stride = 4,
2036 .val_bits = 32,
2037 .max_register = 0x10000,
2038 .fast_io = true,
2039};
2040
2041static const struct qcom_icc_desc sc7280_nsp_noc = {
2042 .config = &sc7280_nsp_noc_regmap_config,
2043 .nodes = nsp_noc_nodes,
2044 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2045 .bcms = nsp_noc_bcms,
2046 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
2047};
2048
2049static struct qcom_icc_bcm * const system_noc_bcms[] = {
2050 &bcm_sn0,
2051 &bcm_sn2,
2052 &bcm_sn7,
2053 &bcm_sn8,
2054};
2055
2056static struct qcom_icc_node * const system_noc_nodes[] = {
2057 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2058 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2059 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2060 [MASTER_PIMEM] = &qxm_pimem,
2061 [MASTER_GIC] = &xm_gic,
2062 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2063 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2064 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2065};
2066
2067static const struct regmap_config sc7280_system_noc_regmap_config = {
2068 .reg_bits = 32,
2069 .reg_stride = 4,
2070 .val_bits = 32,
2071 .max_register = 0x15480,
2072 .fast_io = true,
2073};
2074
2075static const struct qcom_icc_desc sc7280_system_noc = {
2076 .config = &sc7280_system_noc_regmap_config,
2077 .nodes = system_noc_nodes,
2078 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2079 .bcms = system_noc_bcms,
2080 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2081};
2082
2083static const struct of_device_id qnoc_of_match[] = {
2084 { .compatible = "qcom,sc7280-aggre1-noc",
2085 .data = &sc7280_aggre1_noc},
2086 { .compatible = "qcom,sc7280-aggre2-noc",
2087 .data = &sc7280_aggre2_noc},
2088 { .compatible = "qcom,sc7280-clk-virt",
2089 .data = &sc7280_clk_virt},
2090 { .compatible = "qcom,sc7280-cnoc2",
2091 .data = &sc7280_cnoc2},
2092 { .compatible = "qcom,sc7280-cnoc3",
2093 .data = &sc7280_cnoc3},
2094 { .compatible = "qcom,sc7280-dc-noc",
2095 .data = &sc7280_dc_noc},
2096 { .compatible = "qcom,sc7280-gem-noc",
2097 .data = &sc7280_gem_noc},
2098 { .compatible = "qcom,sc7280-lpass-ag-noc",
2099 .data = &sc7280_lpass_ag_noc},
2100 { .compatible = "qcom,sc7280-mc-virt",
2101 .data = &sc7280_mc_virt},
2102 { .compatible = "qcom,sc7280-mmss-noc",
2103 .data = &sc7280_mmss_noc},
2104 { .compatible = "qcom,sc7280-nsp-noc",
2105 .data = &sc7280_nsp_noc},
2106 { .compatible = "qcom,sc7280-system-noc",
2107 .data = &sc7280_system_noc},
2108 { }
2109};
2110MODULE_DEVICE_TABLE(of, qnoc_of_match);
2111
2112static struct platform_driver qnoc_driver = {
2113 .probe = qcom_icc_rpmh_probe,
2114 .remove = qcom_icc_rpmh_remove,
2115 .driver = {
2116 .name = "qnoc-sc7280",
2117 .of_match_table = qnoc_of_match,
2118 .sync_state = icc_sync_state,
2119 },
2120};
2121module_platform_driver(qnoc_driver);
2122
2123MODULE_DESCRIPTION("SC7280 NoC driver");
2124MODULE_LICENSE("GPL v2");